Figure 34.
JTAG Block Diagram
PCIe EP
Edge Connector
JTAG
MUX
Intel MAX 10
Download Cable
JTAG
Analog SW
PD[3:0]
Download
Cable
DIP Switch
DIP Switch
FPGA
Source Select
Enable/Bypass
External
Header
Download Cable
PHY
The on-board Intel FPGA Download Cable II is implemented in an Intel MAX 10 device.
A micro-USB connector connects to a CY7C68013A USB2 PHY provides the data to
Intel MAX 10. This allows configuration of the FPGA using a USB cable directly
connected to a PC running the Intel Quartus Prime software without requiring the
external download cable dongle. An external download cable dongle can also be used
on J12 to configure the FPGA.
A.10. Memory Interfaces
Three independent memory interfaces are supported: Two independent on-board
DDR4 and one dual DIMM sockets for DDR4 or DDR-T.
•
The on-board DDR4 uses five 16Gb DDR4 single rank devices connecting to Bank
2B, 2E for memory component channel 0 and bank 2C, 2F for memory component
channel 1. The total memory size of each channel is 16GB running at 1200MHz.
•
The two 288-pin DIMM sockets interface to bank 3C, 3D for Dual DIMM memory.
These sockets accept DDR4 module. These DIMM will support dual rank at
frequency 1200MHZ 16GB per channel, and will support single rank at 1200MHZ
8GB per channel.
— Some board re-work is required for using DIMM sockets in 2-DPC configuration
or different kinds of DDR4 modules. For more details of the resistor
connections required to be present for the type of configuration used, refer to
board schematic table.
A. Development Kits Components
683288 | 2022.09.22
Intel
®
Agilex
™
I-Series FPGA Development Kit User Guide
48
