Intel AGIB027R29A1E2VR0, User Manual

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A.12. Clock Circuits
All clocks are supplied by three on-board low-jitter programmable clock generator
circuits. The following is the clock connection diagram to the Intel Agilex FPGA. For
detailed clock connections, refer to the schematic.
•
Si5391 provides most of the clocks to the Intel Agilex I-Series FPGA including
reference clocks for memory interfaces, QSFP_DD, and the FPGA SDM/fabric core.
• Si52204 provides the dedicated reference clock as a local clock option for PCIe
Gen5 by selecting the inputs of a clock multiplex/buffer Si53307. Another input of
the clock buffer is from PCIe Edge connector as a system clock of PCIe Gen5.
• Si510 provides a 50MHz clock to System Intel MAX 10 and power Intel MAX 10
devices.
Figure 36. Clock Connection Diagram
2B
2E
2F
2C
3A
SDM
12A
F-Tile
14C
R-Tile
Si53307
Mux_buffer
15C
R-Tile
3B
3C
3D
Intel Agilex FPGA
CXL CONN
Si510
Si52204
Outputs x4
Si5391
Outputs x12
Intel MAX 10
Download Cable & Power
DDR4_COMP_CH0, 33.333 MHz, LVDS
DDR4/T_DDIMM, 33.333 MHz, LVDS
156.25 MHz, LVDS
322.265625 MHz, LVDS
322.265625 MHz, LVDS
156.25 MHz, LVDS
156.25 MHz, LVDS
Sys Refclk from edge Conn, 100 MHz, HCSL
Refclk_PCIe Gen5 100 MHz, HCSL
Si53307
Mux_buffer
Sys Refclk from CXL Conn, 100 MHz, HCSL
Refclk_PCIe Gen5 100 MHz, HCSL
100 MHz, HCSL, for RP in CXL
100 MHz, HCSL, for RP in CXL
CLK, 50 MHz, LVCMOS
OSC_CLK_1, 125 MHz, LVCMOS
DDR4_COMP_CH1, 33.333 MHz, LVDS
SYS_CLK, 100 MHz, LVDS
SYS_CLK_BAK, 100 MHz, LVDS
A.13. System Power
This section describes the Intel Agilex I-Series FPGA development board's power
supply.
A. Development Kits Components
683288 | 2022.09.22
Intel
®
Agilex
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I-Series FPGA Development Kit User Guide
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