Contents
1.1. Block Diagram.......................................................................................................4
1.2. Box Contents........................................................................................................ 7
1.3. Operating Conditions..............................................................................................7
2.2. Development Board Package................................................................................... 8
2.3. Installing the Intel FPGA Download Cable II Driver..................................................... 9
3.1. Applying Power to the Development Board.............................................................. 10
3.2. Default Switch and Jumper Settings....................................................................... 11
3.2.1. Default Setting........................................................................................ 11
3.2.2. Perform Board Restore through Intel Quartus Prime Programmer....................15
3.3. How to Generate a POF Image to Program the Flash................................................. 15
3.4. How to Program the Generated POF Image..............................................................17
3.5. The Required SmartVID QSF Assignments to Compile a Design.................................. 20
4.1.1. Download OpenJDK.................................................................................. 23
4.1.2. Download OpenJFX.................................................................................. 23
4.1.3. Install OpenJDK and OpenJFX.................................................................... 24
4.1.4. Run BTS GUI........................................................................................... 24
4.2.1. The Bottom Info Bar.................................................................................25
4.2.2. The Configure Menu................................................................................. 25
4.2.3. The Sys Info Tab......................................................................................26
4.2.4. The GPIO Tab.......................................................................................... 27
4.2.5. The XCVR Tab..........................................................................................28
4.2.6. The RAM Tab........................................................................................... 32
4.3. Control On-board Clock through Clock Controller GUI............................................... 35
4.4. Monitor On-board Power Regulator through Power Monitor GUI.................................. 36
4.5. BTS Test Areas.................................................................................................... 37
4.6. Identify Test Pass or Fail-based on BTS GUI Test Status.............................................37
A.1. Board Overview...................................................................................................41
A.2. Intel Agilex I-Series FPGA..................................................................................... 42
A.3. PCIe and CXL Interfaces....................................................................................... 42
A.4. MCIO Connector.................................................................................................. 42
A.5. MCIO Cable Assembly Information......................................................................... 44
A.6. Network Interfaces.............................................................................................. 44
A.7. Port Controller.....................................................................................................45
A.8. FPGA Configuration.............................................................................................. 46
Contents
Intel
®
Agilex
™
I-Series FPGA Development Kit User Guide
2
