Intel AGIB027R29A1E2VR0, User Manual

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Figure 33. Port Controller Circuit
U14
VDD1_1
P0_S0_OUT_A
P0_S0_OUT_B
P0_S0_IN_C
P0_MOD_SCL
P0_S0_OUT_D
P0_S0_OUT_C
P0_S1_OUT_B
P0_S1_OUT_A
P0_S1_OUT_D
P0_S1_OUT_C
P0_MOD_SDA
P0_S0_IN_B
P0_S0_IN_A
P0_S1_IN_C
P0_AUX_SDA
P0_AUX_SCL
P0_S1_IN_B
P0_S1_IN_A
P1_S0_OUT_A
P1_S0_OUT_B
P1_S0_IN_A
P1_S0_IN_B
P1_S0_IN_C
P1_MOD_SDA
P1_MOD_SCL
P1_S0_OUT_C
P1_S0_OUT_D
P1_S1_OUT_C
P1_S1_OUT_D
P1_S1_OUT_A
P1_S1_OUT_B
P1_S1_IN_B
P1_S1_IN_C
P1_AUX_SCL
P1_AUX_SDA
P1_S1_IN_A
40
QSFPDD0_3V3_RESET_L 25
QSFPDD0_3V3_LPMODE 25
QSFPDD0_3V3_INT_L 25
QSFPDD0_3V3_MODPRS_L 25
QSFPDD0_I2C_SDA 25
QSFPDD0_I2C_SCL 25
41
38
39
37
35
36
34
33
51
52
44
IO_3p3V
45
VDD1_2
VDD1_3
VDD2_1
VDD2_2
CTRL1
23
24
28
21
31
25
42
53
8
19
30
IO_3p3V
22
29
32
57
27
DAP (GND)
FPC202RHUR
QFN-58
C305
2.2uF
0402
10V
X6S
R137
10.0k, DNI
0402
1%
R135
4.70k
0402
1%
R134
4.70k
0402
1%
R138
10.0k
0402
1%
GND
CAPL
TEST_N
EN
SPI_LED_SY_NC
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
CTRL2
CTRL3
CTRL4
PROTOCOL_SEL
HOST_INT_N
IO_3p3V
9
43
54
20
26
32, 46, 50, 52
32, 46, 50, 52
I2C 8-bit Addr = 0x1E
Place a 1uF and 0.1uF per VDD1 pin Place a 1uF and 0.1uF per VDD2 pin
IO_3p3V
I2C2_SCL
I2C2_SDA
R131
4.70k
0402
1%
IO_3p3V
47 QSFPDD_3V3_PORT_INT_N
47 QSFPDD_3V3_PORT_EN
QSFPDD1_3V3_RESET_L 26
QSFPDD1_3V3_LPMODE 26
QSFPDD1_3V3_INT_L 26
QSFPDD1_3V3_MODPRS_L 26
QSFPDD1_I2C_SDA 26
QSFPDD1_I2C_SCL 26
48
49
56
55
2
1
3
5
4
6
7
17
18
11
13
10
12
14
16
15
50
47
46
IO_3p3V
R133
4.70k
0402
1%
R132
4.70k
0402
1%
C304
0.1uF
0402
25V
X6S
C303
1uF
0402
25V
X6S
C302
0.1uF
0402
25V
X6S
C300
0.1uF
0402
25V
X6S
C299
1uF
0402
25V
X6S
C297
1uF
0402
25V
X6S
C295
1uF
0402
25V
X6S
C298
0.1uF
0402
25V
X6S
C296
0.1uF
0402
25V
X6S
C301
1uF
0402
25V
X6S
A.8. FPGA Configuration
You can use the Intel Quartus Prime Programmer to configure the FPGA with your
SRAM Object File (.sof).
FPGA Configuration Setup
Ensure the following:
•
The Intel Quartus Prime Programmer and the Intel FPGA Download Cable II driver
are installed on the host computer.
• The micro-USB cable is connected to the FPGA development board.
• Power to the board is ON, and no other applications that use the JTAG chain are
running.
Follow these steps:
1. Start the Intel Quartus Prime Programmer.
2. Click Auto Detect to display the devices in the JTAG chain.
3. Click Change File and select the path to the desired .sof.
4. Turn on the Program/Configure option for the added file.
5. Click Start to download the selected file to the FPGA. Configuration is complete
when the progress bar reaches 100%.
Using the Intel Quartus Prime Programmer to configure a device on the board causes
other JTAG-based applications such as the Board Test System and the Power Monitor
to lose their connection to the board. Restart those applications after configuration is
complete.
A. Development Kits Components
683288 | 2022.09.22
Intel
®
Agilex
™
I-Series FPGA Development Kit User Guide
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