IBM z13s, Technical Manual

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Chapter 1. Introducing IBM z13s servers
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In the unlikely case of a permanent core failure, each core can be individually replaced by one
of the available spares. Core sparing is transparent to the operating system and applications.
The N20 has two spares, but the N10 does not offer dedicated spares (the firmware can
determine cores available for sparing).
Simultaneous multithreading
The micro-architecture of the core of z13s servers allows simultaneous execution of two
threads (SMT) in the same zIIP or IFL core, dynamically sharing processor resources such as
execution units and caches. This feature allows a more efficient utilization of the core and
increased capacity. While one of the threads is waiting for a storage access (cache miss), the
other thread that is running simultaneously in the core can use the shared resources rather
than remain idle.
z/OS and z/VM control programs use SMT on z13s servers to optimize their workloads while
providing repeatable metrics for capacity planning and chargeback.
Single instruction multiple data instruction set
The z13s instruction set architecture includes a subset of 139 new instructions for SIMD
execution, which was added to improve efficiency of complex mathematical models and
vector processing. These new instructions allow a larger number of operands to be processed
with a single instruction. The SIMD instructions use the superscalar core to process operands
in parallel, which enables more processor throughput.
Transactional Execution facility
The z13s server, like its predecessor zBC12, has a set of instructions that allows defining
groups of instructions that are run atomically, that is, either all the results are committed or
none are. The facility provides for faster and more scalable multi-threaded execution, and is
known as
hardware transactional memory
.
Out-of-order execution
As with its predecessor zBC12, a z13s server has an enhanced superscalar microprocessor
with OOO execution to achieve faster throughput. With OOO, instructions might not run in the
original program order, although results are presented in the original order. For example,
OOO allows a few instructions to complete while another instruction is waiting. Up to six
instructions can be decoded per system cycle, and up to 10 instructions can be in execution.
Concurrent processor unit conversions
z13s servers support concurrent conversion between various PU types, which provides the
flexibility to meet the requirements of changing business environments. CPs, IFLs, zIIPs,
ICFs, and optional SAPs can be converted to CPs, IFLs, zIIPs, ICFs, and optional SAPs.
Memory subsystem and topology
z13s servers use a new buffered dual inline memory module (DIMM) technology. For this
purpose, IBM has developed a chip that controls communication with the PU, and drives
address and control from DIMM to DIMM. z13s servers use the new DIMM technology, and
carry forward is not supported. The memory subsystem supports 20 DIMMs per drawer and
the DIMM capacities are 16 GB, 32 GB, 64 GB, and 128 GB.
Memory topology provides the following benefits:
򐂰 A RAIM for protection at the dynamic random access memory (DRAM), DIMM, and
memory channel levels
򐂰 A maximum of 4 TB of user configurable memory with a maximum of 5.1 TB of physical
memory (with a maximum of 4 TB configurable to a single LPAR)