IBM z13s, Technical Manual

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Chapter 3. Central processor complex system design
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3.7.1 Overview
Logical partitioning is a function that is implemented by the PR/SM on z13s servers. The z13s
server runs either in LPAR-, or Dynamic Partition Manager mode. Therefore, all system
aspects are controlled by PR/SM functions.
PR/SM is aware of the CPC drawer structure on the z13s server. However, LPARs do not
have this awareness. LPARs have resources that are allocated to them from various physical
resources. From a systems standpoint, LPARs have no control over these physical resources,
but the PR/SM functions do.
PR/SM manages and optimizes allocation and the dispatching of work on the physical
topology. Most physical topology that was previously handled by the operating systems is now
the responsibility of PR/SM.
As shown in 3.5.9, “Processor unit assignment” on page 110, the initial PU assignment is
done during POR by using rules to optimize cache usage. This is the “physical” step, where
CPs, zIIPs, IFLs, ICFs, and SAPs are allocated on the CPC drawers.
When an LPAR is activated, PR/SM builds logical processors and allocates memory for the
LPAR.
Memory allocation has changed from the previous z Systems. IBM System z9® memory used
to be spread across all books. This optimization was done by using a round-robin algorithm
with a number of increments per book to match the number of memory controllers (MCs) per
book. This memory allocation design is driven by performance results, with minimized
variability for most workloads.
With z13 and z13s servers, memory allocation has changed from the model that was used for
the z9. Partition memory is now allocated in a per-CPC-drawer basis and striped across
processor nodes. For more information, see “Memory allocation” on page 112.
Logical processors are dispatched by PR/SM on physical processors. The assignment
topology that is used by PR/SM to dispatch logical processors on physical PUs is also based
on cache usage optimization.
CPC drawers and node level assignments are more important because they optimize L4
cache usage. Therefore, logical processors from a specific LPAR are packed into a CPC
drawer as often as possible.
Then, PR/SM optimizes chip assignments within the assigned CPC drawer (or drawers) to
maximize L3 cache efficiency. Logical processors from an LPAR are dispatched on physical
processors on the same PU chip as much as possible. The number of processors per chip
(eight) matches the number of z/OS processor affinity queues that is used by HiperDispatch,
achieving optimal cache usage within an affinity node.
PR/SM also tries to redispatch a logical processor on the same physical processor to
optimize private cache (L1 and L2) usage.