Evaluation Board Manual
PPC750FX Evaluation Board
Preliminary
CPLD Programming
Page 84 of 115
750FXebm_ch11.fm
June 10, 2003
11.1.2.5 registers2 Program
The following code listing defines the function of the logic in the
registers2 part of the CPLD:
INCLUDE "lpm_ff.inc";
INCLUDE "lpm_mux.inc";
SUBDESIGN registers2
(
sysreset_n
: INPUT;
cstiming_n
: INPUT;
we_n0
: INPUT; -- Dev_we_n[0] from controller
ale
: INPUT; -- for internal latching of address/control
dev_ad[7..0]
: BIDIR; -- when input address/control from system controller it needs latched,
-- " " -- when output to system controller it is data
fpga_cs_n
: INPUT; -- uses lcs_n1
badr[2..0]
: INPUT; -- burst addresses
target/host_n
: INPUT; -- PCI switch
flash_n/sram_sel : INPUT; -- Flash/SRAM switch
bootsmall_n
: INPUT; -- Boot switch
switch_a
: INPUT; -- spare switch A
switch_b
: INPUT; -- spare switch B
ATX_OK_N
: INPUT; -- low if ATX power is on.
ldevR_W_n
: OUTPUT; -- latched directly from muxed address/data bus
lboot_cs_n
: OUTPUT; -- latched directly from muxed address/data bus
led0
: OUTPUT;
led1
: OUTPUT;
led2
: OUTPUT;
cpu0_smi_n
: OUTPUT; -- 2.5V logic to CPU0, resets to high
cpu1_smi_n
: OUTPUT; -- 2.5V logic to CPU1, resets to high
cpu_tben
: OUTPUT; -- 2.5V logic to both CPUs, resets to high
cpu_mcp0
: OUTPUT; -- 2.5V logic to both CPUs, resets to high
cpu_mcp1
: OUTPUT; -- 2.5V logic to both CPUs, resets to high
read_oe
: OUTPUT;
mpp_block_n
: OUTPUT; -- 1 = pass mpp_Xreset pins
)
VARIABLE
ldev_adr[8..3]
: NODE; -- shifting addresses from [7..2] to match other designs.
PLDversion_sel : node;-- register 0
PLDversion[7..0] : NODE;
Register1_sel : NODE;-- register 1
