Evaluation Board Manual
Preliminary
PPC750FX Evaluation Board
750FXebm_ch6.fm
June 10, 2003
Switches
Page 43 of 115
Table 6-7. System Controller Initilization—U24
Switch No.
Signal
Default Setting
Description (0 = ON = closed, 1 = OFF = open)
1
DEV_AD19
OFF
ON = DDR SDRAM address/control signals toggle on falling edge of
DRAM clock.
OFF = DDR SDRAM address/control signals toggle on rising edge of
DRAM clock.
2
DEV_AD21
ON
ON = DDR SDRAM two pipe stages (up to 133MHz SDRAM clock)
OFF = DDR SDRAM three pipe stages (up to 183 MHz SDRAM clock)
3
DEV_AD22
ON
ON = DDR SDRAM read data is synchronized to the MV64360 core clock.
OFF = DDR SDRAM read data is synchronized to the MV64360 FBClkIn
clock signal.
4
DEV_AD23
ON
DDR SDRAM Read Control Logic Delay
ON = Disabled
OFF = Enabled
5
DEV_AD24
ON
DDR SDRAM Read Data Delay
ON = Disabled
OFF = Enabled
6
PCIMODE_TARGET/
HOST_N
OFF
ON = board operates as a PCI Host
OFF = board operates as a PCI Adapter
7
FLASH_N/SRAM_SEL
ON
ON = 8-bit Flash resides at a higher address than the 8-bit SRAM
OFF = 8-bit SRAM resides at a higher address than the 8-bit Flash
Note: This switch can be useful for putting SRAM at the CPU reset vector
during boot ROM code development.
8
DEV_AD14
ON
This switch should always be in the ON position since only 8- or 32-bit
wide devices are available for booting.
