IBM PPC750FX User Manual Download Page 5

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Evaluation Board Manual

Preliminary

PPC750FX Evaluation Board

750FXebmTOC.fm
June 10, 2003

Contents

Page 5 of 115

11. CPLD Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

11.1 Programming—Registers and Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

11.1.1 I/O Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

11.1.2 CPLD Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

11.2 Timing—Registers and Control Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

11.2.1 Maximum Clock Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

11.2.2 Clock-to-Output Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
11.2.3 Pin-to-Pin Signal Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

11.2.4 Setup and Hold Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

12. Bills of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

12.1 Component Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

12.2 Debugging Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

12.3 Auxiliary Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

12.4 Board Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

Revision Log . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Summary of Contents for PPC750FX

Page 1: ...PPC750FX Evaluation Board User s Manual SA14 2720 00 Preliminary June 10 2003 Title Page...

Page 2: ...erformance data contained in this document was determined in a specific or controlled environment and not submitted to any formal IBM test Therefore the results obtained in other operating environment...

Page 3: ...e 21 2 6 PCI Bus 21 2 7 Ethernet 21 2 8 Flash Memory 22 2 9 NVRAM 24 2 10 SRAM 24 2 11 Serial Ports 24 2 12 Logic Analyzer Connections 25 2 13 Power Supply 25 2 13 1 PCI Voltages 25 2 13 2 System Cont...

Page 4: ...1 6 5 System Controller Initialization 42 7 Fuses Batteries Regulators and Fans 45 7 1 On Board Current Monitoring and Variable Voltage Testing 45 7 1 1 1 45V Supplies 45 7 1 2 2 5V Supply 46 7 2 Fan...

Page 5: ...gram 2 78 11 1 2 3 framcs Logic 79 11 1 2 4 decode_block Program 80 11 1 2 5 registers2 Program 84 11 1 2 6 reset_block Program 89 11 1 2 7 misc Logic 93 11 2 Timing Registers and Control Functions 94...

Page 6: ...Evaluation Board Manual PPC750FX Evaluation Board Preliminary Contents Page 6 of 115 750FXebmTOC fm June 10 2003...

Page 7: ...85D09E 36 Table 5 1 External Interrupts 38 Table 6 1 Switches 39 Table 6 2 Reset Pushbutton U5 39 Table 6 3 Reset Pushbutton U53 40 Table 6 4 CPU 0 PLL Configuration U30 40 Table 6 5 CPU 1 PLL Configu...

Page 8: ...s J15 66 Table 10 12 External Clock Input Signal U39 68 Table 10 13 Test Connections 69 Table 11 1 Section Contents 73 Table 11 2 CPLD I O Pin List 73 Table 11 3 CPLD Logic Descriptions 76 Table 11 4...

Page 9: ...50 Figure 9 4 PCI Interrupt Selection Jumper J22 51 Figure 10 1 Connector Location Diagram Top Side 54 Figure 10 2 ATX Power Supply Connector J34 55 Figure 10 3 Ground Connectors J1 J2 J7 J9 J10 J12...

Page 10: ...Evaluation Board Manual PPC750FX Evaluation Board Preliminary Figures Page 10 of 115 750FXebmLOF fm June 10 2003...

Page 11: ...h define the access methods for all memory mapped registers on the board Programming the System Controller outlines the required programming to configure the MV64360 system controller for the board me...

Page 12: ...nctional Specification PowerPC 750FX RISC Microprocessor Embedded Controller User s Manual PowerPC 750FX RISC Microprocessor Evaluation Design Kit User s Manual PowerPC 750FX RISC Microprocessor Evalu...

Page 13: ...ex than would be required for a board design limited to a particular application A customer who is developing his own design using this board design as a guide should simplify the design wherever his...

Page 14: ...ction cache BTIC for eliminating branch delay slots Dispatch unit Full hardware detection of dependencies resolved in the execution units Dispatch two instructions to six independent units system bran...

Page 15: ...metic logical FXU2 shift rotate arithmetic logical Single cycle arithmetic shift rotate logical Multiply and divide support multi cycle Early out multiply Thirty two 32 bit general purpose registers F...

Page 16: ...t for up to 4GB 232 of physical memory Support for big little endian addressing Dual PLLs Allows seamless frequency switching Level 2 L2 cache Internal L2 cache controller and 4K entry tags 512KB data...

Page 17: ...res of the PPC750FX evaluation board are summarized briefly below More detail may be found in Section 2 Board Design on page 19 PCI adapter form factor Two IBM PowerPC 750FX processors Marvell MV64360...

Page 18: ...Evaluation Board Manual PPC750FX Evaluation Board Preliminary Overview Page 18 of 115 750FXebm_ch1 fm June 10 2003...

Page 19: ...essor The PPC750FX evaluation board is based upon the PPC750FX processor See Section 1 1 PowerPC 750FX RISC Microprocessor Features on page 13 for details There are two PPC750FX processors on this boa...

Page 20: ...the PPC750FX Board Clock Generator 33 33MHz Osc Clock Driver External clock MK74CB218 133MHz 2 5V 133MHz 2 5V 133MHz 3 3V CPU 0 CPU 1 CPLD System Controller MV64360 133MHz 3 3V C9531AT 133MHz Clock B...

Page 21: ...RAM operating at 133 33MHz The interface to the SDRAM is through the system controller and is accessed using DRAM chip selects CS0 and CS1 The SDRAM on the board is 72 bits wide and allows the use of...

Page 22: ...16b x 16Mb module 3 3V only for data or code storage Additionally 1MB of SRAM provided as two 512 KB modules can be used in this memory space The board can be set to boot from 8 bit wide Flash with S...

Page 23: ...Configurations Configuration Address Range Module s selected 1 0xFFF00000 to 0xFFFFFFFF 8 bit Flash controlled by BootCS 0xFFE00000 to 0xFFEFFFFF 8 bit SRAM controlled by BootCS 0xFC000000 to 0xFDFFF...

Page 24: ...oller Address space for SRAM is shared with Flash memory See Flash Memory on page 22 for details on how the address space can be configured In addition to the SRAM on the board there are 256KB of addr...

Page 25: ...eloped from the 3 3V PCI voltage 2 13 2 System Controller Voltages The system controller requires four voltages System controller I O 3 3V DRAM 2 5V CPU I O 2 5V System controller logic and Ethernet 1...

Page 26: ...the system controller There is also a 1 25V reference voltage provided to the SDRAM There is no current measurement point provided for this voltage 2 14 Form Factor The PPC750FX board is a full length...

Page 27: ...ip Select Size DDR SDRAM 0x00000000 0x0FFFFFFF SDRAM CS0 and CS1 256MB MV64360 Integrated SRAM 0x42000000 0x4203FFFF n a 256KB FRAM 0xEF500000 0xEF507FFF DevCS3 32KB ST16C2552 UART Channel B 0xEF60000...

Page 28: ...h select R 0 Booted from 8 bit flash or SRAM U17 Switch 6 is ON 1 Booted from 32 bit flash U17 Switch 6 is OFF Table 3 4 Register2 Bit Name R W Description 0 msb CPU1 MCP control R W Asserts the Machi...

Page 29: ...used to control the SRESET and HRESET of pins of the processors and an entire board reset To give software a chance to configure the MPP GPP pins 7 8 11 12 and 24 properly the signals are blocked by...

Page 30: ...Evaluation Board Manual PPC750FX Evaluation Board Preliminary Memory Map Page 30 of 115 750FXebm_ch3 fm June 10 2003...

Page 31: ...of the DDR SDRAM memory on the PPC750FX evaluation board 4 1 1 SDRAM Controller Initialization See Marvell MV64360 1 2 data sheet 4 2 Device Controller Bank Register Settings The following sections de...

Page 32: ...les data N to the cycle that samples data N 1 ALE2Wr 010 Number of Sysclk cycles from ALE de assertion to the assertion of Wr 0 WrLow 010 Number of Sysclk cycles that Wr 0 is active WrHigh 010 Number...

Page 33: ...ples data N to the cycle that samples data N 1 ALE2Wr 010 Number of Sysclk cycles from ALE de assertion to the assertion of Wr 0 WrLow 010 Number of Sysclk cycles that Wr 0 is active WrHigh 010 Number...

Page 34: ...data N to the cycle that samples data N 1 ALE2Wr 101 Number of Sysclk cycles from ALE de assertion to the assertion of Wr 0 WrLow 000 Number of Sysclk cycles that Wr 0 is active WrHigh 000 Number of...

Page 35: ...data N to the cycle that samples data N 1 ALE2Wr 010 Number of Sysclk cycles from ALE de assertion to the assertion of Wr 0 WrLow 100 Number of Sysclk cycles that Wr 0 is active WrHigh 100 Number of S...

Page 36: ...the first read data is sampled Acc2Next 010 Number of Sysclk cycles in a burst read access between the cycle that samples data N to the cycle that samples data N 1 ALE2Wr 010 Number of Sysclk cycles...

Page 37: ...or by undervoltage on the 3 3V supply Under software control using registers in the CPLD each processor can be reset individually or the entire board can be reset 5 2 Interrupts The system controller...

Page 38: ...pts MPP Controller Pin Active Sensitivity Description 25 level UART Channel A 26 level UART Channel B 27 level Ethernet PHY 28 level PCI Intr A 29 level PCI Intr B 30 level PCI Intr C 31 level PCI Int...

Page 39: ...n switch at U5 pulls the PWRGD signal to ground causing a reset of the board Table 6 1 Switches Location Function Page U5 Reset pushbutton 39 U17 U24 System controller initialization 42 U30 CPU 0 PLL...

Page 40: ...have no effect 6 3 CPU 0 PLL Configuration An 8 position DIP switch at location U30 configures the PLL for the first PPC750FX processor U1 Table 6 3 Reset Pushbutton U53 Signal Description 0 ON close...

Page 41: ...able 6 5 CPU 1 PLL Configuration Switches U35 Switch No Signal Default Setting Description 0 ON closed 1 OFF open 1 PLL_CONFIG0 ON Refer to the latest version of the PowerPC 750FX RISC Microprocessor...

Page 42: ...ts of the 7 bit IIC address of the Serial ROM the MV64360 can use for initialization ON ON address 0b1010000 Serial EEPROM U36 ON OFF reserved OFF ON address 0b1010001 Serial EEPROM U55 OFF OFF reserv...

Page 43: ...AM read data is synchronized to the MV64360 core clock OFF DDR SDRAM read data is synchronized to the MV64360 FBClkIn clock signal 4 DEV_AD23 ON DDR SDRAM Read Control Logic Delay ON Disabled OFF Enab...

Page 44: ...Evaluation Board Manual PPC750FX Evaluation Board Preliminary Switches Page 44 of 115 750FXebm_ch6 fm June 10 2003...

Page 45: ...0X bus voltages can be monitored for current drain In addition external supplies can be connected in place of the fixed on board regulators to perform variable voltage testing Removal of zero ohm resi...

Page 46: ...one fan provided on the board This fan is mounted on the processor heatsinks and cools both of the processor chips See Figure 7 2 The system controller chip has a heatsink attached but no fan The proc...

Page 47: ...nd viewed looking into the sockets Table 8 1 Displays Location Name Color Description DS1 DS2 LED0 LED1 Green CPLD status User programmable by setting bits in a CPLD register DS3 RED_LED Red Board pro...

Page 48: ...Evaluation Board Manual PPC750FX Evaluation Board Preliminary Displays Page 48 of 115 750FXebm_ch8 fm June 10 2003...

Page 49: ...The location type and function for all jumpers on the board are described in the following sections Table 9 1 Jumpers Location Function Page J8 32 bit Flash write protection 50 J16 Ignore Fan 50 J22 P...

Page 50: ...e causes the power to the processors and system controller to be shut down The J16 jumper can be used to avoid this power shutdown if the user wishes to continue operation following a fan failure It i...

Page 51: ...stem controller to one or more of the four PCI interface interrupts This a 2x4 Berg type header Figure 9 4 PCI Interrupt Selection Jumper J22 Table 9 4 PCI Interrupt Selection J22 J22 Description Fact...

Page 52: ...Evaluation Board Manual PPC750FX Evaluation Board Preliminary Jumpers Page 52 of 115 750FXebm_ch9 fm June 10 2003...

Page 53: ...in Section 10 12 and shown in Figure 10 13 Table 10 1 Connectors Location Function Page J34 ATX Power 55 J4 CPU Fan Power 56 J11 RISCWatch JTAG 57 J13 RJ11 Serial Ports 1 Right and 2 Left 63 J14 Syste...

Page 54: ...ide J13 J25 J19 1 2 38 37 J15 1 2 38 37 J14 1 2 38 37 J20 J4 2 1 J34 U39 B12 B94 Note PCI contacts A1 through A94 mirror the B1 B94 contacts on the bottom side of the card 2 1 12 L R 8 7 12 8 7 2 1 8...

Page 55: ...ing the ATX power on pushbutton U53 will have no effect Figure 10 2 ATX Power Supply Connector J34 Table 10 2 ATX Power Signals J34 Pin Name Comment 1 3 3V Tolerance 4 2 3 3V Tolerance 4 3 GND 4 5V To...

Page 56: ...0 3 Fan Power There is one connector available at J4 for powering the fan that cools the two processor chips Figure 10 3 Ground Connectors J1 J2 J7 J9 J10 J12 J17 J18 J23 J24 Table 10 3 Ground Connect...

Page 57: ...ger The RISCWatch JTAG debugger connects to the board through a 2x8 header Figure 10 5 RISCWatch JTAG Connector J11 Table 10 5 RISCWatch Signals J11 Pin Signal Name 1 TDO 2 unused 3 TDI 4 TRST_N 5 unu...

Page 58: ...nd two LEDs The ports are identified as 1 and 2 Both ports can be configured for Fast 10 100 Mbps Ethernet interfaces and can be used with Category 5 Unshielded Twisted Pair UTP cable Figure 10 6 Ethe...

Page 59: ...ctor J25 Table 10 7 PCI Connector Signals J25 Pin Signal Pin Signal B1 12V A1 TRST B2 TCK A2 12V B3 GND A3 TMS B4 TDO A4 TDI B5 5V A5 5V B6 5V A6 INTA B7 INTB A7 INTC B8 INTD A8 5V B9 PRSNT1 A9 Reserv...

Page 60: ...3 C BE2 A33 3 3V B34 GND A34 FRAME B35 IRDY A35 GND B36 3 3V A36 TRDY B37 DEVSEL A37 GND B38 GND A38 STOP B39 LOCK A39 3 3V B40 PERR A40 Reserved B41 3 3V A41 Reserved B42 SERR A42 GND B43 3 3V A43 PA...

Page 61: ...68 AD63 A68 AD62 B69 AD61 A69 GND B70 3 3V I O A70 AD 60 B71 AD 59 A71 AD58 B72 AD57 A72 GND B73 GND A73 AD56 B74 AD55 A74 AD54 B75 AD53 A75 3 3V I O B76 GND A76 AD52 B77 AD51 A77 AD50 B78 AD49 A78 GN...

Page 62: ...nector and appropriate downloading software This is a 2x5 Berg type connector B92 Reserved A92 Reserved B93 Reserved A93 GND B94 GND A94 Reserved Figure 10 8 CPLD JTAG Connector J26 Table 10 8 CPLD JT...

Page 63: ...port interfaces are provided by the ST16C2552 attached to the system controller and support only four RS 232 signals Table 10 9 describes the pin assignments for Serial Ports 1 and 2 Note that DTR app...

Page 64: ...Address Connector J14 Table 10 10 System Controller Device Address Signals J14 Pin Analyzer Signal Name 1 unused 2 unused 3 GND 4 unused 5 addr_pod0 CLK ALE 6 addr_pod1 CLK unused 7 addr_pod0 D15 DEV_...

Page 65: ...r_pod0 D5 DEV_ADR 21 28 addr_pod1 D5 DEV_ADR 5 29 addr_pod0 D4 DEV_ADR 20 30 addr_pod1 D4 DEV_ADR 4 31 addr_pod0 D3 DEV_ADR 19 32 addr_pod1 D3 DEV_ADR 3 33 addr_pod0 D2 DEV_ADR 18 34 addr_pod1 D2 DEV_...

Page 66: ...or J15 Table 10 11 Memory Control Signals J15 Pin Analyzer Signal Name 1 unused 2 unused 3 GND 4 unused 5 cntl_pod0 CLK unused 6 cntl_pod1 CLK unused 7 cntl_pod0 D15 BADR 2 8 cntl_pod1 D15 TESTPIN_A 9...

Page 67: ...SET_2 5_N 27 cntl_pod0 D5 BIG_FLASH_CS_N 28 cntl_pod1 D5 unused 29 cntl_pod0 D4 SMALL_FLASH_HI_CS_N 30 cntl_pod1 D4 TESTPIN_D 31 cntl_pod0 D3 SRAM_HI_CS_N 32 cntl_pod1 D3 TESTPIN_B 33 cntl_pod0 D2 REA...

Page 68: ...scillator connected to this board mounted SMA connector The oscillator output should have 3 3V logic levels The input impedance to this connector is approximately 50 Note Board rework is required to u...

Page 69: ...ype of test connection is called an ehole or test access via These test connections have a very small pad and center hole The reference designators for eholes are Unn where nn are numbers To determine...

Page 70: ...9 U3 System Controller MPP5 TP30 U3 System Controller MPP14 TP31 U3 System Controller MPP27 TP32 U3 System Controller MPP20 TP33 U2 750FX QREQ1 TP34 U3 System Controller MPP22 TP35 U3 System Controlle...

Page 71: ...1 of 115 Figure 10 13 Test Connection Locations TP15 TP12 TP9 TP17 TP21 TP34 TP32 TP35 TP31 U26 TP27 TP29 TP24 TP30 TP28 TP23 TP25 TP8 TP16 TP20 TP22 TP6 TP7 TP39 TP38 TP37 TP36 TP33 TP2 TP1 TP10 TP5...

Page 72: ...Evaluation Board Manual PPC750FX Evaluation Board Preliminary Connectors Page 72 of 115 750FXebm_ch10 fm June 10 2003...

Page 73: ...programming within the CPLD 11 1 1 I O Pin List Table 11 2 lists all of the signals entering and exiting the CPLD module The module pin number and I O function are shown Note Pins that are labeled as...

Page 74: ...GND 26 Gnd dev_adr 5 27 Bidir dev_adr 6 28 Bidir dev_adr 7 29 Bidir sysreset_n 30 Output mpp1_hreset_n 31 Input NOFAN_N 32 Output sram_cs_n 33 Output VCCIO1 34 Power small_flash_cs_n 35 Output read_n...

Page 75: ...we_n 0 63 Input lcs_n 0 64 Input bootsmall_n 65 Input VCCIO2 66 Power badr 2 67 Input rw_sreset 68 Input jtag_chkstop_n 69 Output cpu_tben 70 Output cpu1_smi_n 71 Output cpu0_smi_n 72 Output TDO 73 Ou...

Page 76: ...adr 3 96 Bidir dev_adr 4 97 Bidir ldev_addr 20 98 Input cpufan_ok_n 99 Input ldev_addr 19 100 Input Table 11 3 CPLD Logic Descriptions Section Description Page Top Level Block Diagram 1 First three of...

Page 77: ..._n sram_sel bootsmall_n switch_a ldevr_w_n lboot_cs_n led0 led1 led2 cpu0_smi_n cpu1_smi_n cpu_tben cpu_mcp0 cpu_mcp1 mpp_block_n dev_adr 7 0 nvram_burst_cs_n sysreset_n cstiming_n we_n0 ale fpga_cs_n...

Page 78: ...i_reset_n pld25mhz mpp_reset_out_n mpp_block_n pwrgd dev_adr0 sysreset_n cpu0_chkstop_n cpu1_chkstop_n mpp_reset_2ms_n powergood serial_eeprom jtag_chkstop_n sysreset 25Mclk rw_hreset rw_sreset rw_trs...

Page 79: ...6 2003 framcs bdf Project top badr0 qadr0 badr1 qadr1 badr2 qadr2 qadr2 qadr1 qadr0 VCC sysclock INPUT VCC lcs_n 3 INPUT VCC sysreset INPUT VCC cstiming_n INPUT GND badr0 INPUT GND badr1 INPUT GND ba...

Page 80: ...l address ordering Device Addr0 is the LSB flash_n sram_sel INPUT bootsmall_n INPUT ldevR_W_n INPUT Dev_We_n0 INPUT nvram_burst_cs_n INPUT small_flash_lo_cs_n OUTPUT default lboot_cs_n swappable to lc...

Page 81: ...flash SRAM big flash 1 1 big flash small flash SRAM del_nvramcs lpm_ff WITH LPM_WIDTH 12 enable aset LPM_FFTYPE DFF del_uart lpm_ff WITH LPM_WIDTH 10 enable aset LPM_FFTYPE DFF halfclk_ lpm_ff WITH L...

Page 82: ...ldev_addr 19 Chip select 0 upperarea and lowerarea toparea lcs_n 0 ldev_addr 20 ldev_addr 19 botarea lcs_n 0 ldev_addr 20 ldev_addr 19 upperarea lcs_n 0 ldev_addr 20 ldev_addr 19 lowerarea lcs_n 0 ld...

Page 83: ...ram_lo_cs_n CSTiming_n FLASH SRAM BIG loarea BIG FLASH SRAM lowerarea SRAM FLASH BIG bootarea BIG SRAM FLASH botarea big_flash_cs_n CSTiming_n bootsmall_n lcs_n 0 bootsmall_n lbootcs_n sram_cs_n sram_...

Page 84: ...INPUT PCI switch flash_n sram_sel INPUT Flash SRAM switch bootsmall_n INPUT Boot switch switch_a INPUT spare switch A switch_b INPUT spare switch B ATX_OK_N INPUT low if ATX power is on ldevR_W_n OUT...

Page 85: ...ev 7 0 NODE led0_node node led1_node node led2_node node cpu0_smi_n_node node cpu1_smi_n_node node cpu_tben_node node cpu_mcp0_node node cpu_mcp1_node node data_sel 3 0 NODE which bus to read bux_muxe...

Page 86: ...er1 data 4 switch_b spare switch B Register1 data 3 switch_a spare switch A Register1 data 2 target host_n PCI switch Register1 data 1 flash_n sram_sel Flash SRAM switch Register1 data 0 bootsmall_n B...

Page 87: ...t Register3 clock we_n0 Register3 data 7 0 dev_ad 7 0 Register3 data 0 dev_ad 0 mpp_block_n 1 pass mpp_Xreset pins mpp_block_n Register3 q 0 mpp_block_n 1 pass mpp_Xreset pins Register 0 if badr 2 0 B...

Page 88: ...xer data 3 7 0 Register3 q 7 0 bux_muxer data 4 7 0 BoardRev 7 0 bux_muxer sel data_sel output enable for read from FPGA only read_oe cstiming_n ldevR_W_n Register1_sel Register2_sel Register3_sel PLD...

Page 89: ...st INPUT mpp_reset_2ms_n INPUT mpp0_hreset_n INPUT mpp0_sreset_n INPUT mpp1_hreset_n INPUT mpp1_sreset_n INPUT mpp_reset_out_n INPUT initact INPUT pgd INPUT target host_n INPUT serial_eeprom INPUT pci...

Page 90: ...sloclk3 1 0 dff sloclk3_ node BEGIN If target mode then pci_reset_n causes reset_n If host mode ignore pci_reset_n sysreset_n pci_reset_n target host_n ATX_OK_N mpp_reset_2ms_n del_pgd sysreset sysre...

Page 91: ...pgd_ data 5 del_pgd_ q 4 del_pgd_ data 6 del_pgd_ q 5 del_pgd_ data 7 del_pgd_ q 6 del_pgd del_pgd_ q 0 del_pgd_ q 1 del_pgd_ q 2 del_pgd_ q 3 del_pgd_ q 4 del_pgd_ q 5 del_pgd_ q 6 del_pgd_ q 7 this...

Page 92: ...w_trst del_rw_trst 1 d del_rw_trst 0 q cpu_trst_n_ initact serial_eeprom del_rw_trst 0 q del_rw_trst 1 q sysreset_n del_sysreset_n treset logicend this reset signal is output to PCI bus this is also t...

Page 93: ...t_n mpp_block_n pld25mhz pld25mhz mpp_reset_2ms_n del_powergood VCC pld25mhz INPUT VCC pwrgd INPUT VCC dev_adr0 INPUT VCC sysreset_n INPUT VCC cpu0_chkstop_n INPUT VCC cpu1_chkstop_n INPUT serial_eepr...

Page 94: ...g Frequency Allowed Maximum Frequency period pld25mhz 25MHz 166 67MHz 6ns dev_we_n 0 None 181 82MHz 5 5ns pld_sysclk 133 33MHz 185 19MHz 5 4ns Table 11 5 Clock to Output Time Output Signal Clock Longe...

Page 95: ...9 400 9 400 led_red_n pld25mhz 9 500 9 400 led0 dev_we_n 0 5 700 5 700 led1 dev_we_n 0 5 700 5 700 led2 dev_we_n 0 5 700 5 700 nvram_cs_n ale 18 500 18 500 nvram_cs_n pld_sysclk 23 100 17 700 pci_rese...

Page 96: ..._adr 0 8 700 5 600 badr 0 dev_adr 1 8 700 5 600 badr 0 dev_adr 2 8 700 5 600 badr 0 dev_adr 3 8 700 5 600 badr 0 dev_adr 4 8 700 5 600 badr 0 dev_adr 5 8 700 5 600 badr 0 dev_adr 6 8 700 5 600 badr 0...

Page 97: ...cpufan_ok_n NOFAN_N 5 100 5 100 cstiming_n big_flash_cs_n 5 700 5 700 cstiming_n dev_adr 0 8 800 8 800 cstiming_n dev_adr 1 8 800 8 800 cstiming_n dev_adr 2 8 800 8 800 cstiming_n dev_adr 3 8 800 8 8...

Page 98: ..._n 0 sram_hi_cs_n 5 200 5 200 lcs_n 0 textpin_d 5 400 5 400 lcs_n 1 dev_adr 0 8 500 8 500 lcs_n 1 dev_adr 1 8 500 8 500 lcs_n 1 dev_adr 2 8 500 8 500 lcs_n 1 dev_adr 3 8 500 8 500 lcs_n 1 dev_adr 4 8...

Page 99: ...00 pci_reset_n cpu_trst_n 14 500 14 100 pci_reset_n cpu0_hreset_n 11 200 10 400 pci_reset_n cpu1_hreset_n 14 900 14 500 pci_reset_n led_red_n 5 200 5 200 pci_reset_n sysreset 10 200 10 200 pci_reset_n...

Page 100: ...0 1 300 0 500 cstiming_n dev_we_n 0 3 200 0 100 dev_adr 0 ale 1 400 0 400 dev_adr 0 dev_we_n 0 1 000 0 800 dev_adr 0 pld25mhz 6 700 8 600 dev_adr 1 ale 1 500 0 300 dev_adr 1 dev_we_n 0 1 100 0 700 de...

Page 101: ...le 12 5 the component is not assembled if the DNP column contains TRUE In some cases installation of DNP parts requires the removal of installed parts and constitutes a change in the design of the boa...

Page 102: ...s 7 995 inches from the 0 0 datum Note that it is possible for components to have negative coordinate values Figure 12 1 Example of a Component Placement List in the Schematics Table 12 2 Component Pl...

Page 103: ...the example table is shown in Figure 12 1 Note The appearance of the scales as shown in the example figure is representative only The actual appearance will vary from board to board due to constraint...

Page 104: ...ermination Adapter Vendor 1 HP Vendor 1 P N E5346A Table 12 4 Auxiliary Materials in Kit Quantity Part Number Supplier Description 2 AM29LV040B 70JC AMD Flash EEPROM 512K x 8 3V 1 1 382811 6 AMP Tyco...

Page 105: ...Materials Page 105 of 115 12 4 Board Bill of Materials Table 12 5 provides a complete list of all components used to manufacture the board assembly In addition all components that appear in the schem...

Page 106: ...C380 C382 C395 C397 C410 C412 C438 C441 C457 C459 C460 C462 C481 C483 C484 C486 C490 C492 C494 C495 C497 C499 C509 SMEC0402 AVX 0402ZC104MAT2A 0 1U 10 C102 C133 C136 C159 C160 C165 C166 C312 SMEC0402...

Page 107: ...1C 1 J11 HDRM2X8_JT AGCLIP AMP TYCO 147062 3 RJ11 12_DUAL _SHIELD 1 J13 RJ11_1X2 MOLEX 44248 0093 3 J14 J15 J19 CONN_MICTO R38 AMP 2 767004 2 2 J8 J16 BERG2X1 AMP 104350 1 RJ45ENE TXFRM_ LED 1 J20 RJ4...

Page 108: ...2 R235 R245 R249 R260 R276 R279 R280 R285 R286 R292 R302 R407 R414 R417 R422 R429 R436 R439 R441 SMER0402 PHYCOMP 9C1A040222R0FL HF3 120 7 R82 R96 R100 R330 SMER0402 YAGEO AMERICA 9C04021A1100FL HF3 D...

Page 109: ...2X 49 9 10 R264 R265 R269 R270 R289 R296 R301 R305 R306 R463 SMER0402 PHYCOMP 9C1A040249R9FL HF3 PANASONIC ERJ 2RKF49R9X 340K 2 R273 R313 SMER0402 VENKEL CR0402 16W 3403FT 0 15 R278 R281 R284 R287 R29...

Page 110: ...I2VR25 030 2 U19 U20 TSSOP48P5 FAIRCHILD 74VCX16373MTD 1 U2 750FXLOWER IBM PPC750FX GB2533T 2 U9 U21 TSSOP16P65 MAXIM MAX3232CUE CLOCK_ BUF_1TO 4 1 U25 SOE08_280R ICS ICS553MI 2 U26 U28 EHOLE DO NOT O...

Page 111: ...1 4 1 U54 SOT235 PHILIPS SEMICONDUCT ORS 74HC1G14GV FAIRCHILD NC7S14M5X ALLIED ELECTRONICS 263 0257 74LVC1G 14 1 U56 SOT235 PHILIPS SEMICONDUCT ORS 74LVC1G14GV TI SN74LVC1G14D BVR DIGIKEY 296 11607 1...

Page 112: ...01X PHYCOMP 9C1A04021001F LHF3 TRUE 909K 4 R232 R234 R255 R258 SMER0402 PANASONIC ERJ2RKF9093X TRUE 1 21M 2 R272 R311 SMER0402 VENKEL CR0402 16W 1214FT TRUE 4 7K 15 R283 R452 R457 R475 R498 R500 R514...

Page 113: ...C component location 101 connectors 53 auxiliary power 55 CPLD JTAG 62 Ethernet 58 external clock input 68 fan power 56 GND ground 56 memory control 66 PCI 59 RISCWatch 57 serial ports 63 system cont...

Page 114: ...nector 59 R real time clock 24 regulators 45 resets 37 S serial ports 24 switches 39 ATX power on pushbutton 40 PLL 0 configuration 40 PLL 1 configuration 41 reset pushbutton 39 system controller init...

Page 115: ...tion Board Manual Preliminary PPC750FX Evaluation Board 750FXebm_revlog fm June 10 2003 Revision Log Page 115 of 115 Revision Log Revision Date Contents of Modification 06 10 03 Initial creation of th...

Page 116: ......

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