Evaluation Board Manual
PPC750FX Evaluation Board
Preliminary
Board Design
Page 20 of 115
750FXebm_ch2.fm
June 10, 2003
2.2 Board Clocking
The clock architecture of the PPC750FX board is illustrated in
Figure 2-2. Clock Distribution on the PPC750FX Board
Clock
Generator
33.33MHz Osc
Clock
Driver
External clock
MK74CB218
133MHz @ 2.5V
133MHz @ 2.5V
133MHz @ 3.3V
CPU 0
CPU 1
CPLD
System
Controller
MV64360
133MHz @ 3.3V
C9531AT
133MHz
Clock
Buffer
25MHz Osc
25MHz
CPLD
Clock
Multiplier
125 MHz
Dual
Ethernet
PHY
25MHz
25MHz
ICS93V857
2
10
DDR SDRAM
BCM5222
Dual
UART
3.6864MHz Osc
STI6C2552
Clock
Driver
(see Note)
Note : Rework to the board is required to use the external oscillator input.
