Evaluation Board Manual
Preliminary
PPC750FX Evaluation Board
750FXebm_ch3.fm
June 10, 2003
Memory Map
Page 27 of 115
3. Memory Map
Table 3-1 provides a summary of the board address space usage. For details about address space usage
relating to the processor registers, refer to the
PPC750FX Embedded Processor User’s Manual.
3.1 CPLD Register Definitions
This section provides description by bit for each of the CPLD registers.
Each CPLD register is 8 bits wide. In the tables below, the most significant bit is bit 0, and the least significant
bit is bit 7. The CPLD source code uses the reverse bit ordering.
Table 3-1. Board Address Space Usage
Peripheral
Start Address
End Address
Chip Select
Size
DDR SDRAM
0x00000000
0x0FFFFFFF
SDRAM CS0 and CS1
256 MB
MV64360 Integrated SRAM
0x42000000
0x4203FFFF
n/a
256 KB
FRAM
0xEF500000
0xEF507FFF
DevCS3
32 KB
ST16C2552 UART Channel B
0xEF600000
0xEF600007
DevCS2
8 B
ST16C2552 UART Channel A
0xEF600008
0xEF60000F
DevCS2
8 B
CPLD Registers
0xEF700000
0xEF700004
DevCS1
5 B
MV64360 Registers
0xF1000000
0xF100FFFF
n/a
64KB
32-bit Flash
0xFC000000
0xFDFFFFFF
DevCS0
32MB
SRAM
0xFFE00000
0xFFEFFFFF
BootCS
1 MB
8-bit Flash
0xFFF00000
0xFFFFFFFF
BootCS
1 MB
Note: The base addresses of peripherals attached to the MV64360 system controller device are software dependent. The values in the
table above are used by the PPC750FX Evaluation Kit Software. Other software environments may use different values for the
peripheral base addresses.
Table 3-2. Register0
Bit
Name
R/W
Description
0:7
CPLD Revision
R
Revision level of CPLD code
