IBM PPC750FX, User Manual

Page: 97 / 116

Evaluation Board Manual
Preliminary PPC750FX Evaluation Board
750FXebm_ch11.fm
June 10, 2003 CPLD Programming
Page 97 of 115
badr[2] dev_adr[5] 8.700 5.600
badr[2] dev_adr[6] 8.700 5.600
badr[2] dev_adr[7] 8.700 5.600
badr[2] nvram_cs_n 14.700 14.700
badr[2] uart_cs_n 7.100 5.600
badr[2] write_n 7.900 5.600
bootsmall_n big_flash_cs_n 5.300 5.300
bootsmall_n small_flash_cs_n 5.300 5.300
bootsmall_n small_flash_hi_cs_n 5.300 5.300
bootsmall_n sram_cs_n 5.300 5.300
bootsmall_n sram_hi_cs_n 5.300 5.300
bootsmall_n textpin_d 5.500 5.500
cpu0_chkstop_n jtag_chkstop_n 5.600 5.600
cpu1_chkstop_n jtag_chkstop_n 5.600 5.600
cpufan_ok_n led_red_n 5.100 5.100
cpufan_ok_n NOFAN_N 5.100 5.100
cstiming_n big_flash_cs_n 5.700 5.700
cstiming_n dev_adr[0] 8.800 8.800
cstiming_n dev_adr[1] 8.800 8.800
cstiming_n dev_adr[2] 8.800 8.800
cstiming_n dev_adr[3] 8.800 8.800
cstiming_n dev_adr[4] 8.800 8.800
cstiming_n dev_adr[5] 8.800 8.800
cstiming_n dev_adr[6] 8.800 8.800
cstiming_n dev_adr[7] 8.800 8.800
cstiming_n fpga_cs_n 5.700 5.700
cstiming_n nvram_cs_n 15.900 15.900
cstiming_n read_n 5.700 5.700
cstiming_n small_flash_cs_n 5.700 5.700
cstiming_n small_flash_hi_cs_n 5.700 5.700
cstiming_n sram_cs_n 5.700 5.700
cstiming_n sram_hi_cs_n 5.700 5.700
cstiming_n textpin_d 5.900 5.900
cstiming_n uart_cs_n 7.200 5.700
cstiming_n write_n 8.000 5.700
dev_we_n[0] uart_cs_n 6.900 5.400
dev_we_n[0] write_n 7.700 5.800
Table 11-6. Pin-to-Pin Signal Delay (Continued)
Source Destination Longest Delay (ns) Shortest Delay (ns)