HP X Class 500/550MHz, Reference Manual

Page: 38 / 149

38 Chapter 2
System Board
Chipset
Integrated DRAM Controller
• Up to 2 GB with registered DIMMs (4 x 512
MB)
1
.
• Supports up to four double-sided DIMMs (8
rows memory).
• 64-bit data interface with ECC support
(SDRAM only).
• Unbuffered and Registered SDRAM
(synchronous) DRAM support (x-1-1-1
access at 100 MHz).
• Enhanced SDRAM Open Page Architecture
Support for 16-, 64-, 128- and 256-Mbit
DRAM devices with 2k, 4k and 8k page
sizes.
Power Management Functions
• Stop Clock Grant and Halt special cycle
translation (host to PCI bus).
• “Deep Green” Desktop supports for system
suspend/resume (i.e., DRAM and power-on
suspend).
• SDRAM self-refresh power down support in
suspend mode.
• Independent, internal dynamic clock gating
reduces average power dissipation.
• Static STOP CLOCK support.
• Power-on Suspend mode.
• Suspend to DRAM.
• ACPI-compliant power management.
PCI Bus Interface
• PCI Rev. 2.1, 3.3V and 5V, 33 MHz interface
compliant.
• PCI Parity Generation Support.
• Data streaming support from PCI to
DRAM.
• Delayed Transaction support for
PCI-DRAM Reads.
• Supports concurrent CPU, AGP and PCI
transactions to main memory.
Supporting I/O Bridge
• System Management Bus (SMB) with
support for DIMM
Serial Presence Detect (SPD).
• PCI-ISA Bridge (PIIX4E).
• Power Management Support.
• 3.3V core and mixed 5V, 3.3V I/O and
interface to the 2.5V CPU signals via
open-drain output buffers.
Packaging/Voltage
• 492-pin BGA.
• 3.3V core and mixed 3.3V and GTL I/O.
1. 82443GX Host Bridge Controller also supports 2 GB of unbuffered DIMMs (256Mbit
technology).
Table 2-2. Features Available in the Host Bridge/Controller
Feature Feature