124
Chapter 5
Tests and Error Messages
Order in Which the Tests Are Performed
59h
Initialize POST display service
5Ah
Display prompt “Press F2 to enter SETUP”
5Bh
Disable CPU cache
5Ch
Test RAM between 512 and 640 KB
60h
Test extended memory
62h
Test extended memory address lines
64h
Jump to UserPatch1
66h
Configure advanced cache registers
67h
Initialize Multi Processor APIC
68h
Enable external and CPU caches
69h
Setup System Management Mode (SMM) area
6Ah
Display external L2 cache size
6Ch
Display shadow-area message
6Eh
Display possible high address for UMB recovery
70h
Display error messages
72h
Check for configuration errors
74h
Test real-time clock
76h
Check for keyboard errors
7Ah
Test for key lock on
7Ch
Set up hardware interrupt vectors
7Eh
Initialize coprocessor if present
80h
Disable onboard Super I/O ports and IRQs
81h
Late POST device initialization
82h
Detect and install external RS 232 ports
83h
Configure non-MCD IDE controllers
Checkpoint Code
POST Routine Description
Summary of Contents for X Class 500/550MHz
Page 6: ...6 Contents ...
Page 8: ...8 Figures ...
Page 15: ...15 1 System Overview ...
Page 66: ...66 Chapter2 System Board Devices on the ISA Bus ...
Page 96: ...96 Chapter3 Interface Boards and Mass Storage Drivers Connectors and Sockets ...
Page 134: ...134 Chapter5 Tests and Error Messages Beep Codes ...
Page 135: ...135 A Regulatory Information and Warranty ...
Page 146: ...146 AppendixA Regulatory Information and Warranty HP Hardware Warranty ...