Circuit Functional Descriptions
Model 3585A
6-24
pulse train becomes the Cycle Start (CS) signal that enters the Frac N chip. U6 and U7 take
the input signal after it has been divided by 2 or 3 and divides it by 5 to form the Chip Clock
(CC) for the Frac N chip. U2B and U3 are to ensure synchronization of the pulse train that
will go to the phase detector. Since the accuracy of the entire section is based on measuring
the phase difference between this pulse train and the 100 kHz reference, it is crucial that the
timing of this pulse be tightly controlled. A latch clock is also generated for the API hex
latch on A32.
The A32, Analog, board begins with a phase detector whose output is determined by the
phase difference between the signal from A33 and a 100 kHz reference from A21 . This puls
ed output charges C9 of the integrator. Q32 and Q34 act as sample switches, transferring the
voltage on C9 first to C 1 3 and then to C14 and through a unity gain buffer to A3 1 as the dc
tuning voltage. Two FET switches are used to reduce spurs due to a single switch acting as a
capacitor.
The remainder of the A32 board is the bias and API circuitry. The duration of the individual
API's is programmed by the Frac N chip and is latched onto the board by U 1 . API l is 1 1100
of the phase detect current. Each successive API is 1 110 of the preceding one. The bias and
API currents are summed and form the current that discharges C9 in the integrator, ready
ing it for the next phase detector current pulse. The rest of this board is timing and switching
for the various currents and the sample/hold.
The Frac N VTO tune voltage from A32 enters A3 1 and is buffered (gain
=
1 .5) and then low
pass filtered. From this point the Frac N Error voltage goes to the Sum Loop (A27). In the
multiple loop mode, this voltage also tunes the 35-60 MHz VTO on the A3 1 board, which is
then buffered and goes back to the A33 board to close the loop . The 35-60 MHz signal is
also -;- 20 to achieve the 1 .75-3 .00 MHz signal necessary as a reference on the A28 board.
Notice that in single loop, the 100-1 40 MHz signal from A24 enters A3 1 and is divided by
four to attain the 25-35 MHz used to close the loop when in single loop.
6·24. LO Control (A34)
This board controls the LO and, therefore, the sweep. LODA lines 0 thru 4 enter the board
and are directed, via gates and flip-flops, to the trigger circuitry, the fractional N section, the
Step Loop and/or the A/D.
This board contains the trigger circuitry, with a choice of external or line (60 Hz) trigger.
Unlock indications from the various loops all enter this board and light LED's to indicate an
unlock situation. These are also OR'ed together to signal an "LO Unlocked" on the display.
This board also contains a voltage regulator and additional circuitry for providing power
supplies to other boards . Finally, a 200 usec clock is generated for signaling A/D conver
sions .
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Summary of Contents for 3585A
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