Circuit Functional Descriptions
Model 3585A
6-20
A28 also has a lock detector circuit which checks the tuning voltage to see that it falls within
± 0.27 volts . A tuning voltage outside of this range indicates an unlocked condition in the
Sum Loop. Finally, the (H)SLSCN signal (Single Loop Scan, high for single loop (SL) and
low for multiple loop (ML» is converted from SL = + 3 . 8V and ML = OV to SL = - 1 5V and
ML = + 14V for mode switch control.
The A27, First LO VTO Control, board is where all of the tuning voltages from the various
loops are summed together in order to generate a single tuning voltage for the First LO
VCO. When in single loop, the tuning voltage is determined by the Fractional N Loop error
tuning voltage alone. The Step and Sum Loops are not involved as such. In this case (SL),
the Fractional N Loop error voltage enters the board, passes through a buffer , some scaling
and a unity gain amplifier. In single loop, Q8 acts as a closed switch (whereas Q7 is open)
and allows the tuning voltage to pass to the VTO (A22) of the Sum Loop.
In multiple loop, Q7 is closed and Q8 is open. The Sum Loop Pretune (which is the tuning
voltage from the Step Loop) and a scaled down Fractional N Error voltage are summed
together and filtered to smooth the result and rid it of its high frequency components. The
filtered result is then summed with the Sum Loop Error voltage from A28. Q7 allows this
final result to pass on to the First LO VTO (A22).
6·22. Step Loop (A23 and A26)
The Step Loop provides a signal from 98 to 1 38 MHz in
I
MHz steps. It is based on a simple
+- N PLL and much of it is very similar to what we have already seen. In fact, A23 is almost
identical to the A22 board in the Sum Loop. The only difference is some biasing. A23 is an
oscillator, gain amplifier, and a pair of buffered outputs. One output goes to the Sum Loop
and the other goes to the next board in the Step Loop, A26, Step Phase Detector.
The A26, Step/Phase Detector, board has three inputs. One is from the A23 board (98 to
1 38 MHz), a second from the A21 Reference board (90 MHz). These two inputs are buf
fered, then mixed to get a resultant output frequency from 8 to 48 MHz. This signal is then
low pass filtered to rid it of its high frequency components and is shaped to get more of a
square wave. This square wave then enters a programmable
+-
N counter. N is an integer
from 8 to 48 and is programmed to always yield an output of 1 MHz. This 1 MHz signal is
then phase-compared with the third input to this board. The third input signal is a 10 MHz
reference, from the A21 board, that has gone through a +- 1 O counter to yield 1 MHz.
The phase detector outputs a pulse whose width is determined by the difference in phase of
the two input signals. This pulse then enters an integrator and sample and hold circuit. The
output from the sample and hold circuit is buffered, exits the board and feeds back to A23
to tune the Step Loop VCO. Another output goes to the Sum Loop A27 board where it
becomes part of the tuning voltage for the First LO VTO on the A22 board. That same out
put is also checked by a comparator to make sure that the tune voltage is not too high or
low, indicating an unlocked situation.
6·23. Fractional N Loop (A3 l , A32 and A33)
Fractional N technology gives the -hp- 3585A the additional frequency accuracy that
+-
N
does not give. Before going into the implementation of Fractional N in the -hp- 3585A, we
will briefly discuss the concept of fractional N synthesis. We will begin with our basic
+-
N
PLL . See Figure 6-9. Standard Phase Lock Loop.
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Summary of Contents for 3585A
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