1089
TCNT0—Timer Counter 0
TCNT1—Timer Counter 1
H'FF74 (W), H'FF75 (R)
H'FFA2 (W), H'FFA3 (R)
WDT0
WDT1
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Bit
Initial value
R/W
:
:
:
Note: TCNT is write-protected by a password to prevent accidental overwriting.
For details see section 15.2.5, Notes on Register Access.
RSTCSR—Reset Control/Status Register
H'FF76 (W), H'FF77 (R)
WDT0
7
WOVF
0
R/(W)
*
6
RSTE
0
R/W
5
RSTS
0
R/W
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
Notes:
*
Only 0 can be written to these bits (to clear these flags).
TCNT is write-protected by a password to prevent accidental overwriting.
For details see section 15.2.5, Notes on Register Access.
Watchdog timer overflow flag
0
[Clearing]
Writing 0 to WOVF after reading TCSR when WOVF=1.
1
[Setting]
When, in watchdog timer mode, TCNT overflows (H’FF
→
H’00).
Reset select
0
Power-on reset.
1
Manual reset.
Reset enable
0
No internal reset on TCNT overflow.
*
1
Internal reset performed on TCNT overflow.
Note:
*
The LSI is not internally reset, but TCNT and TCSR
in WDT are reset.
Bit
Initial value
R/W
:
:
:
