1012
TCR0—Timer Control Register 0
TCR1—Timer Control Register 1
TCR2—Timer Control Register 2
TCR3—Timer Control Register 3
H'FF68
H'FF69
H'FDC0
H'FDC1
TMR0
TMR1
TMR2
TMR3
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
CMFB interrupt request (CMIB) disabled
CMFB interrupt request (CMIB) enabled
0
1
0
Compare match interrupt enable B
CMFA interrupt request (CMIA) disabled
CMFA interrupt request (CMIA) enabled
1
Compare match interrupt enable A
OVF interrupt request (OVI) disabled
OVF interrupt request (OVI) enabled
0
1
Timer overflow interrupt enable
Internal clock: Counting on falling edge of ø/8192
Internal clock: Counting on falling edge of ø/8
Internal clock: Counting on falling edge of ø/64
Clock input disabled
Counter clear 1, 0
Clock select 2 to 0
0
1
0
CKS0
0
CKS2 CKS1
0
1
1
External clock: Counting on both rising and falling edges
External clock: Counting on rising edge
External clock: Counting on falling edge
Channel 0: Counting on TCNT1 overflow signal
*
Channel 1: Counting on TCNT0 compare match A
*
Channel 2: Counting on TCNT3 overflow signal
*
Channel 3: Counting on TCNT2 compare match A
*
0
1
0
1
0
1
1
Cleared by rising edge of external reset input
Cleared by compare match A
Cleared by compare match B
Clearing disabled
0
1
0
CCLR0
CCLR1
0
1
1
Note:
*
No countup clock is generated if the channel 0 (channel 2) clock input is the TCNT1
(TCNT3) overflow signal, and that the channel 1 (channel 3) clock input is the TCNT0
(TCNT2) compare match signal. Do not, therefore, attempt to make such a setting.
Bit
Initial value
R/W
:
:
:
