1082
DMACR0A—DMA Control Register 0A
DMACR0B—DMA Control Register 0B
DMACR1A—DMA Control Register 1A
DMACR1B—DMA Control Register 1B
H'FF62
H'FF63
H'FF64
H'FF65
DMAC
DMAC
DMAC
DMAC
Bit
DMACRA
Initial value
R/W
Full address mode
:
:
:
:
15
DTSZ
0
R/W
14
SAID
0
R/W
13
SAIDE
0
R/W
12
BLKDIR
0
R/W
11
BLKE
0
R/W
10
—
0
R/W
9
—
0
R/W
8
—
0
R/W
Block Direction/Block Enable
0
Transfer in normal mode
1
0
1
0
1
Transfer in block transfer mode,
destination is block area
Transfer in normal mode
Transfer in block transfer mode,
source is block area
Source Address Increment/Decrement
0
MARA is fixed
1
0
1
0
1
MARA is incremented after a data transfer
MARA is fixed
MARA is decremented after a data transfer
Data Transfer Size
0
Byte-size transfer
1
Word-size transfer
• When DTSZ = 0, MARA is incremented by 1 after a transfer
• When DTSZ = 1, MARA is incremented by 2 after a transfer
• When DTSZ = 0, MARA is decremented by 1 after a transfer
• When DTSZ = 1, MARA is decremented by 2 after a transfer