1020
SSR0—Serial Status Register 0
SSR1—Serial Status Register 1
SSR2—Serial Status Register 2
SSR3—Serial Status Register 3
SSR4—Serial Status Register 4
H'FF7C
H'FF84
H'FF8C
H'FDD4
H'FDDC
SCI0
SCI1
SCI2
SCI3
SCI4
7
TDRE
1
R/(W)
*
1
6
RDRF
0
R/(W)
*
1
5
ORER
0
R/(W)
*
1
4
FER
0
R/(W)
*
1
3
PER
0
R/(W)
*
1
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Transmit data register empty
0
[Clearing]
(1) Writing 0 to TDRE after reading TDRE=1;
(2) When data written to TDR by DMAC or DTC by TXI interrupt request;
1
[Setting]
(1) When SCR TE bit=0;
(2) When data is sent from TDR to TSR and data can be written to TDR.
Receive data register full
0
[Clearing]
(1) Writing 0 to RDRF after reading RDRF=1.
(2) After reading RDR data by DMAC or DTC by RXI interrupt request.
1
[Setting]
When receive data is sent from RSR to RDR on normal completion of serial
receive operation.
Overrun error
0
[Clearing]
*
1
Writing 0 to ORER after reading ORER=1.
1
[Setting]
On completion of next serial receive operation when RDRF=1.
*
2
Framing error
0
[Clearing]
*
1
Writing 0 to FER after reading FER=1.
1
[Setting]
When SCI checks if the stop bit at the end of receive data is 1 on completion of receiving, the stop bit is found to be 0.
*
2
Parity error
0
[Clearing]
*
1
Writing 0 to PER after reading PER=1;
1
[Setting]
When receiving, when the number of 1s in receive data plus parity bit does not match the even or odd
parity specified in the SMR O/E bit.
*
2
Transmit end
0
[Clearing]
(1) Writing 0 to TDRE flag after reading TDRE=1;
(2) When data is written to TDR by DMAC or DTC by TXI interrupt request.
1
[Setting]
(1) When SCR TE bit=0;
(2) When TDRE=1 at transfer of last bit of any byte of serial transmit character.
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a
framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent
serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial
transmission cannot be continued, either.
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent
serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission
cannot be continued, either.
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when
the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data
will be lost.
Multiprocessor bit
0
[Clearing]
*
When data “multiprocessor bit = 0” is received.
1
[Setting]
When data “multiprocessor bit = 1” is received.
Note: *
The existing status is continued when, in multi-
processor format, the SCR RE bit is cleared to 0.
Multiprocessor bit transfer
0
Transfer data “multiprocessor bit = 0”.
1
Transfer data “multiprocessor bit = 1”.
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0.
2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also,
subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked
synchronous mode, serial transmission cannot be continued, either.
Bit
Initial value
R/W
:
:
:
Note: Only 0 can be written to these bits (to clear these flags).
