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20.2

Register Descriptions

20.2.1

D/A Data Registers 0 to 3 (DADR0 to DADR3)

7

0

R/W

6

0

R/W

5

0

R/W

4

0

R/W

3

0

R/W

0

0

R/W

2

0

R/W

1

0

R/W

Bit

Initial value

R/W

:

:

:

D/A data registers 0 to 3 (DADR0 to DADR3) are 8-bit readable/writable registers that store data
to be converted. When analog output is enabled, the value in the D/A data register is converted
and output continuously at the analog output pin.

The D/A data registers are initialized to H'00 by a reset and in hardware standby mode.

20.2.2

D/A Control Register 01 and 23 (DACR01 and DACR23)

7

DAOE1

0

R/W

6

DAOE0

0

R/W

5

DAE

0

R/W

4

—

1

—

3

—

1

—

0

—

1

—

2

—

1

—

1

—

1

—

Bit

Initial value

R/W

:

:

:

DACR01 and DACR23 are an 8-bit readable/writable register that controls the operation of the
D/A converter module.

DACR01 and DACR23 are initialized to H'1F by a reset and in hardware standby mode.

Bit 7—D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output.

Bit 7
DAOE1

Description

0

Analog output DA1 (DA3) is disabled

(Initial value)

1

D/A conversion is enabled on channel 1. Analog output DA1 (DA3) is enabled

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Summary of Contents for H8S/2631

Page 1: ...H8S 2633 Series H8S 2633 HD6432633 H8S 2632 HD6432632 H8S 2631 HD6432631 H8S 2633 F ZTAT HD64F2633 Hardware Manual ADE 602 165A Rev 2 0 4 14 00 Hitachi Ltd ...

Page 2: ...of bodily injury such as aerospace aeronautics nuclear power combustion control transportation traffic safety equipment or medical equipment for life support 4 Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating operating supply voltage range heat radiation characteristics installation conditions and other characteristics Hita...

Page 3: ... available providing a quick and flexible response to conditions from ramp up through full scale volume production even for applications with frequently changing specifications On chip supporting functions include a 16 bit timer pulse unit TPU programmable pulse generator PPG 8 bit timer 14 bit PWM timer PWM watchdog timer WDT serial communication interface SCI IrDA A D converter D A converter and...

Page 4: ...ons Classified by Function Table 2 3 Instructions classified by Function Notes on TAS Instruction added 66 2 10 Usage Note Added 68 3 2 1 Mode Control Register MDCR Bit 7 description amended 75 3 4 Pin Functions in Each Operating Mode Table 3 3 Pin Functions in Each Mode amended 76 to 78 3 5 Address Map in Each Operating Mode Figure 3 1 Memory Map in Each Operating Mode in the H8S 2633 Note 2 adde...

Page 5: ...Figure 7 39 Bus Released State Transition Timing amended 209 210 8 1 3 Overview of Functions Table 8 1 Overview of DMAC Functions SCI transfer source names amended 290 291 8 7 Usage Notes DMAC Register Access during Operation added Figure 8 40 and figure 8 41 added 296 9 1 2 Block Diagram Figure 9 1 Block Diagram of DTC amended 310 311 9 3 3 DTC Vector Table Table 9 4 Interrupt Sources DTC Vector ...

Page 6: ...its 1 and 0 amended 646 16 3 5 IrDA Operation Figure 16 22 IrDA Transmit and Receive Operations amended 653 to 658 16 5 Usage Notes Operation in Case of Mode Transition added Switching from SCK Pin Function to Port Pin Function added 18 1 1 Features Formatless description deleted 692 693 18 1 2 Block Diagram Description amended Figure 18 1 Block Diagram of I2 C Bus Interface Dedicated formatless c...

Page 7: ...ple Flowcharts Figure 18 14 Flowchart for Master Transmit Mode Example amended Figure 18 15 Flowchart for Master Receive Mode Example amended 734 to 736 18 3 10 Initialization of Internal State Added 736 737 739 740 18 4 Usage Notes Table 18 6 I2 C Bus Timing SCL and SDA Output amended Table 18 7 Permissible SCL Rise Time tSr Values ø 25 MHz added to time indication Table 18 8 I2 C Bus Timing with...

Page 8: ...rial Control Register X SCRX Amended 801 22 6 1 Boot Mode Automatic SCI Bit Rate Adjustment Bit rate amended 803 804 22 6 2 User Program Mode Description amended 805 to 812 22 7 Programming Erasing Flash Memory Completely revised 821 22 11 1 Socket Adapter Pin Correspondence Diagram Figure 22 17 Socket Adapter Pin Correspondence Diagram amended 822 22 11 2 Programmer Mode Operation Table 22 11 Set...

Page 9: ...Each Mode WDT module stop mode description amended 860 861 24 2 2 System Clock Control Register SCKCR Description amended 871 24 6 3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Table 24 5 Oscillation Stabilization Time Settings 25 MHz added 25 2 Power supply voltage and operating frequency range Deleted Following item numbers amended 880 to 887 25 2 DC Characteristi...

Page 10: ...mory Characteristics Added 925 927 942 A 1 Instruction List Table A 1 Instruction Set Notes on TAS Instruction added MULXU and MULXS instruction execution states amended 956 957 A 2 Instruction Codes Table A 2 Instruction Codes Notes on TAS Instruction added 974 975 A 4 Number of States Required for Instruction Execution Table A 5 Number of Cycles in Instruction Execution Notes on TAS Instruction ...

Page 11: ... 4 2 General Registers 31 2 4 3 Control Registers 32 2 4 4 Initial Register Values 34 2 5 Data Formats 35 2 5 1 General Register Data Formats 35 2 5 2 Memory Data Formats 37 2 6 Instruction Set 38 2 6 1 Overview 38 2 6 2 Instructions and Addressing Modes 39 2 6 3 Table of Instructions Classified by Function 41 2 6 4 Basic Instruction Formats 48 2 7 Addressing Modes and Effective Address Calculatio...

Page 12: ...4 74 3 3 2 Mode 5 74 3 3 3 Mode 6 74 3 3 4 Mode 7 74 3 4 Pin Functions in Each Operating Mode 75 3 5 Address Map in Each Operating Mode 75 Section 4 Exception Handling 79 4 1 Overview 79 4 1 1 Exception Handling Types and Priority 79 4 1 2 Exception Handling Operation 80 4 1 3 Exception Vector Table 80 4 2 Reset 82 4 2 1 Overview 82 4 2 2 Types of Reset 82 4 2 3 Reset Sequence 83 4 2 4 Interrupts ...

Page 13: ...mes 113 5 5 Usage Notes 114 5 5 1 Contention between Interrupt Generation and Disabling 114 5 5 2 Instructions that Disable Interrupts 115 5 5 3 Times when Interrupts are Disabled 115 5 5 4 Interrupts during Execution of EEPMOV Instruction 116 5 6 DTC and DMAC Activation by Interrupt 116 5 6 1 Overview 116 5 6 2 Block Diagram 116 5 6 3 Operation 117 Section 6 PC Break Controller PBC 119 6 1 Overvi...

Page 14: ...144 7 2 6 Pin Function Control Register PFCR 146 7 2 7 Memory Control Register MCR 149 7 2 8 DRAM Control Register DRAMCR 151 7 2 9 Refresh Timer Counter RTCNT 153 7 2 10 Refresh Time Constant Register RTCOR 153 7 3 Overview of Bus Control 154 7 3 1 Area Partitioning 154 7 3 2 Bus Specifications 155 7 3 3 Memory Interfaces 156 7 3 4 Interface Specifications for Each Area 157 7 3 5 Chip Select Sign...

Page 15: ...1 Bus Arbitration 204 7 11 1 Overview 204 7 11 2 Operation 204 7 11 3 Bus Transfer Timing 205 7 12 Resets and the Bus Controller 205 Section 8 DMA Controller 207 8 1 Overview 207 8 1 1 Features 207 8 1 2 Block Diagram 208 8 1 3 Overview of Functions 209 8 1 4 Pin Configuration 211 8 1 5 Register Configuration 212 8 2 Register Descriptions 1 Short Address Mode 213 8 2 1 Memory Address Registers MAR...

Page 16: ...nction 282 8 5 13 DMAC Multi Channel Operation 283 8 5 14 Relation Between External Bus Requests Refresh Cycles the DTC and the DMAC 285 8 5 15 NMI Interrupts and DMAC 286 8 5 16 Forced Termination of DMAC Operation 287 8 5 17 Clearing Full Address Mode 288 8 6 Interrupts 289 8 7 Usage Notes 290 Section 9 Data Transfer Controller DTC 295 9 1 Overview 295 9 1 1 Features 295 9 1 2 Block Diagram 296 ...

Page 17: ...on 10 I O Ports 327 10 1 Overview 327 10 2 Port 1 332 10 2 1 Overview 332 10 2 2 Register Configuration 333 10 2 3 Pin Functions 335 10 3 Port 3 347 10 3 1 Overview 347 10 3 2 Register Configuration 347 10 3 3 Pin Functions 350 10 4 Port 4 353 10 4 1 Overview 353 10 4 2 Register Configuration 354 10 4 3 Pin Functions 354 10 5 Port 7 355 10 5 1 Overview 355 10 5 2 Register Configuration 356 10 5 3 ...

Page 18: ...ions 390 10 11 4 MOS Input Pull Up Function 391 10 12 Port F 392 10 12 1 Overview 392 10 12 2 Register Configuration 393 10 12 3 Pin Functions 395 10 13 Port G 397 10 13 1 Overview 397 10 13 2 Register Configuration 398 10 13 3 Pin Functions 400 Section 11 16 Bit Timer Pulse Unit TPU 403 11 1 Overview 403 11 1 1 Features 403 11 1 2 Block Diagram 407 11 1 3 Pin Configuration 408 11 1 4 Register Con...

Page 19: ...11 6 1 Input Output Timing 476 11 6 2 Interrupt Signal Timing 480 11 7 Usage Notes 484 Section 12 Programmable Pulse Generator PPG 495 12 1 Overview 495 12 1 1 Features 495 12 1 2 Block Diagram 496 12 1 3 Pin Configuration 497 12 1 4 Registers 498 12 2 Register Descriptions 499 12 2 1 Next Data Enable Registers H and L NDERH NDERL 499 12 2 2 Output Data Registers H and L PODRH PODRL 500 12 2 3 Nex...

Page 20: ...tion Timing 533 13 3 2 Compare Match Timing 534 13 3 3 Timing of External RESET on TCNT 536 13 3 4 Timing of Overflow Flag OVF Setting 536 13 3 5 Operation with Cascaded Connection 537 13 4 Interrupts 538 13 4 1 Interrupt Sources and DTC Activation 538 13 4 2 A D Converter Activation 538 13 5 Sample Application 539 13 6 Usage Notes 540 13 6 1 Contention between TCNT Write and Clear 540 13 6 2 Cont...

Page 21: ... Interval Timer Operation 578 15 3 3 Timing of Setting Overflow Flag OVF 578 15 3 4 Timing of Setting of Watchdog Timer Overflow Flag WOVF 579 15 4 Interrupts 580 15 5 Usage Notes 580 15 5 1 Contention between Timer Counter TCNT Write and Increment 580 15 5 2 Changing Value of CKS2 to CKS0 581 15 5 3 Switching between Watchdog Timer Mode and Interval Timer Mode 581 15 5 4 System Reset by WDTOVF Si...

Page 22: ... 17 1 Overview 659 17 1 1 Features 659 17 1 2 Block Diagram 660 17 1 3 Pin Configuration 661 17 1 4 Register Configuration 662 17 2 Register Descriptions 664 17 2 1 Smart Card Mode Register SCMR 664 17 2 2 Serial Status Register SSR 666 17 2 3 Serial Mode Register SMR 668 17 2 4 Serial Control Register SCR 670 17 3 Operation 671 17 3 1 Overview 671 17 3 2 Pin Connections 671 17 3 3 Data Format 673...

Page 23: ...3 6 IRIC Setting Timing and SCL Control 728 18 3 7 Operation Using the DTC 729 18 3 8 Noise Canceler 730 18 3 9 Sample Flowcharts 730 18 3 10 Initialization of Internal State 734 18 4 Usage Notes 736 Section 19 A D Converter 745 19 1 Overview 745 19 1 1 Features 745 19 1 2 Block Diagram 746 19 1 3 Pin Configuration 747 19 1 4 Register Configuration 748 19 2 Register Descriptions 749 19 2 1 A D Dat...

Page 24: ...ation 779 21 4 Usage Notes 779 Section 22 ROM 781 22 1 Features 781 22 2 Overview 782 22 2 1 Block Diagram 782 22 2 2 Mode Transitions 783 22 2 3 On Board Programming Modes 784 22 2 4 Flash Memory Emulation in RAM 786 22 2 5 Differences between Boot Mode and User Program Mode 787 22 2 6 Block Configuration 788 22 3 Pin Configuration 788 22 4 Register Configuration 789 22 5 Register Descriptions 78...

Page 25: ... Status Polling 831 22 11 8 Programmer Mode Transition Time 831 22 11 9 Notes on Memory Programming 832 22 12 Flash Memory and Power Down States 833 22 12 1 Note on Power Down States 833 22 13 Flash Memory Programming and Erasing Precautions 834 22 14 Note on Switching from F ZTAT Version to Mask ROM Version 839 Section 23 Clock Pulse Generator 841 23 1 Overview 841 23 1 1 Block Diagram 841 23 1 2...

Page 26: ...Software Standby Mode 870 24 6 3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode 871 24 6 4 Software Standby Mode Application Example 872 24 6 5 Usage Notes 873 24 7 Hardware Standby Mode 873 24 7 1 Hardware Standby Mode 873 24 7 2 Hardware Standby Mode Timing 874 24 8 Watch Mode 874 24 8 1 Watch Mode 874 24 8 2 Exiting Watch Mode 875 24 8 3 Notes 875 24 9 Sub Sleep Mod...

Page 27: ...cution 976 A 6 Condition Code Modification 990 Appendix B Internal I O Register 996 B 1 Addresses 996 B 2 Functions 1006 Appendix C I O Port Block Diagrams 1104 C 1 Port 1 Block Diagram 1104 C 2 Port 3 Block Diagram 1110 C 3 Port 4 Block Diagram 1118 C 4 Port 7 Block Diagram 1119 C 5 Port 9 Block Diagram 1126 C 6 Port A Block Diagram 1127 C 7 Port B Block Diagram 1131 C 8 Port C Block Diagram 1132...

Page 28: ...xviii Appendix G Package Dimensions 1154 ...

Page 29: ...configuration include DMA controller DMAC data transfer controller DTC bus masters ROM and RAM memory a16 bit timer pulse unit TPU programmable pulse generator PPG 8 bit timer 14 bit PWM timer PWM watchdog timer WDT serial communication interface SCI IrDA A D converter D A converter and I O ports It is also possible to incorporate an on chip PC bus interface IIC as an option On chip ROM is availab...

Page 30: ...modes Normal mode 64 kbyte address space cannot be used in the H8S 2633 Series Advanced mode 16 Mbyte address space Bus controller Address space divided into 8 areas with bus specifications settable independently for each area Choice of 8 bit or 16 bit access space for each area 2 state or 3 state access space can be designated for each area Number of program wait states can be set for each area B...

Page 31: ...tput or inverse output setting possible 8 bit timer 4 channels 8 bit up counter external event count possible Time constant register 2 2 channel connection possible Watchdog timer 2 channels Watchdog timer or interval timer selectable Operation using sub clock supported WDT1 only 14 bit PWM timer PWM Maximum of 4 outputs Resolution 1 16384 Maximum carrier frequency 390 6 kHz operating at 25 MHz Se...

Page 32: ...nnels I O ports 73 I O pins 16 input only pins Memory PROM or mask ROM High speed static RAM Product Name ROM RAM H8S 2633 256 kbytes 16 kbytes H8S 2632 192 kbytes 12 kbytes H8S 2631 128 kbytes 8 kbytes Interrupt controller Nine external interrupt pins NMI IRQ0 to IRQ7 72 internal interrupt sources including options Eight priority levels settable Power down state Medium speed mode Sleep mode Modul...

Page 33: ...lock pulse generator On chip PLL circuit 1 2 4 Input clock frequency 2 to 25 MHz Packages 120 pin plastic TQFP TFP 120 128 pin plastic QFP FP 128 I2 C bus interface IIC 2 channels optional Conforms to I2 C bus interface type advocated by Philips Single master mode slave mode Possible to determine arbitration lost conditions Supports two slave addresses Product lineup Model Name Mask ROM Version F ...

Page 34: ...3 PO11 TIOCD0 TCLKB A23 P12 PO10 TIOCC0 TCLKA A22 P11 PO9 TIOCB0 DACK1 A21 P10 PO8 TIOCA0 DACK0 A20 P77 TxD3 P76 RxD3 P75 TMO3 SCK3 P74 TMO2 MRES P73 TMO1 TEND1 CS7 P72 TMO0 TEND0 CS6 SYNCI P71 TMR23 TMC23 DREQ1 CS5 P70 TMR01 TMC01 DREQ0 CS4 PG4 CS0 PG3 CS1 PG2 CS2 PG1 CS3 OE IRQ7 PG0 CAS IRQ6 PF7 ø PF6 AS LCAS PF5 RD PF4 HWR PF3 LWR ADTRG IRQ3 PF2 LCAS WAIT BREQO PF1 BACK BUZZ PF0 BREQ IRQ2 RAM T...

Page 35: ... TxD4 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 AVCC Vref P40 AN0 P41 AN1 P42 AN2 P43 AN3 P44 AN4 P45 AN5 P46 AN6 DA0 P47 AN7 DA1 P90 AN8 P91 AN9 P92 AN10 P93 AN11 P94 AN12 P95 AN13 P96 AN14 DA2 P97 AN15 DA3 AVSS P70 TMRI01 TMCI01 DREQ0 CS4 P71 TMRI23 TMCI23 DREQ1 CS5 P72 TMO0 TEND0 CS6 SYNCI P73 TMO1 TEND1 CS7 P74 TMO2 MRES P75 TMO3 SCK3 P76 RxD3 P7...

Page 36: ...1 CS3 OE IRQ7 PG0 CAS IRQ6 P37 TxD4 NC NC P36 RxD4 P35 SCK1 SCK4 SCL0 IRQ5 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P34 RxD1 SDA0 P33 TxD1 SCL1 VSS P32 SCK0 SDA1 IRQ4 PVCC2 P31 RxD0 IrRxD P30 TxD0 IrTxD PD7 D15 PD6 D14 PD5 D13 PD4 D12 PD3 D11 PD2 D10 PD1 D9 PVCC1 PD0 D8 VSS PE7 D7 PE6 D6 PE5 D5 PE4 D4 PE3 D3 PE2 D2 PE1 D1 ...

Page 37: ... VSS VSS VSS VSS 12 16 A8 A8 PB0 A8 TIOCA3 PB0 TIOCA3 13 17 PVCC1 PVCC1 PVCC1 PVCC1 14 18 A9 A9 PB1 A9 TIOCB3 PB1 TIOCB3 15 19 A11 A11 PB3 A11 TIOCD3 PB3 TIOCD3 17 21 A12 A12 PB4 A12 TIOCA4 PB4 TIOCA4 18 22 A13 A13 PB5 A13 TIOCB4 PB5 TIOCB4 19 23 A14 A14 PB6 A14 TIOCA5 PB6 TIOCA5 20 24 A15 A15 PB7 A15 TIOCB5 PB7 TIOCB5 21 25 A16 A16 PA0 A16 PA0 22 26 A17 A17 PA1 A17 TxD2 PA1 TxD2 23 27 A18 A18 PA2...

Page 38: ...A2 PWM2 IRQ1 P16 PO14 TIOCA2 PWM2 IRQ1 P16 PO14 TIOCA2 PWM2 IRQ1 P16 PO14 TIOCA2 PWM2 IRQ1 33 39 P17 PO15 TIOCB2 PWM3 TCLKD P17 PO15 TIOCB2 PWM3 TCLKD P17 PO15 TIOCB2 PWM3 TCLKD P17 PO15 TIOCB2 PWM3 TCLKD 34 40 D0 PE0 D0 PE0 D0 PE0 35 41 D1 PE1 D1 PE1 D1 PE1 36 42 D2 PE2 D2 PE2 D2 PE2 37 43 D3 PE3 D3 PE3 D3 PE3 38 44 D4 PE4 D4 PE4 D4 PE4 39 45 D5 PE5 D5 PE5 D5 PE5 40 46 D6 PE6 D6 PE6 D6 PE6 41 47 ...

Page 39: ...5 60 66 P36 RxD4 P36 RxD4 P36 RxD4 P36 RxD4 67 NC NC NC NC 68 NC NC NC NC 61 69 P37 TxD4 P37 TxD4 P37 TxD4 P37 TxD4 62 70 PG0 CAS IRQ6 PG0 CAS IRQ6 PG0 CAS IRQ6 PG0 IRQ6 63 71 PG1 CS3 OE IRQ7 PG1 CS3 OE IRQ7 PG1 CS3 OE IRQ7 PG1 IRQ7 64 72 PG2 CS2 PG2 CS2 PG2 CS2 PG2 65 73 PG3 CS1 PG3 CS1 PG3 CS1 PG3 66 74 PG4 CS0 PG4 CS0 PG4 CS0 PG4 67 75 WDTOVF WDTOVF WDTOVF WDTOVF 68 76 PLLVCC PLLVCC PLLVCC PLLV...

Page 40: ...RQ2 99 NC NC NC NC 100 NC NC NC NC 91 101 AVCC AVCC AVCC AVCC 92 102 Vref Vref Vref Vref 93 103 P40 AN0 P40 AN0 P40 AN0 P40 AN0 94 104 P41 AN1 P41 AN1 P41 AN1 P41 AN1 95 105 P42 AN2 P42 AN2 P42 AN2 P42 AN2 96 106 P43 AN3 P43 AN3 P43 AN3 P43 AN3 97 107 P44 AN4 P44 AN4 P44 AN4 P44 AN4 98 108 P45 AN5 P45 AN5 P45 AN5 P45 AN5 99 109 P46 AN6 DA0 P46 AN6 DA0 P46 AN6 DA0 P46 AN6 DA0 100 110 P47 AN7 DA1 P4...

Page 41: ...TMRI23 TMCI23 DREQ1 CS5 P71 TMRI23 TMCI23 DREQ1 112 122 P72 TMO0 TEND0 CS6 SYNCI P72 TMO0 TEND0 CS6 SYNCI P72 TMO0 TEND0 CS6 SYNCI P72 TMO0 TEND0 SYNCI 113 123 P73 TMO1 TEND1 CS7 P73 TMO1 TEND1 CS7 P73 TMO1 TEND1 CS7 P73 TMO1 TEND1 114 124 P74 TMO2 MRES P74 TMO2 MRES P74 TMO2 MRES P74 TMO2 MRES 115 125 P75 TMO3 SCK3 P75 TMO3 SCK3 P75 TMO3 SCK3 P75 TMO3 SCK3 116 126 P76 RxD3 P76 RxD3 P76 RxD3 P76 R...

Page 42: ...LL capacitance External capacitance pin for on chip PLL oscillator XTAL Input Connects to a crystal oscillator See section 23 Clock Pulse Generator for typical connection diagrams for a crystal oscillator and external clock input EXTAL Input Connects to a crystal oscillator The EXTAL pin can also input an external clock See section 23 Clock Pulse Generator for typical connection diagrams for a cry...

Page 43: ...e chip is reset MRES Input Manual reset When this pin is driven low a transmission is made to manual reset mode STBY Input Standby When this pin is driven low a transition is made to hardware standby mode BREQ Input Bus request Used by an external bus master to issue a bus request to the H8S 2633 Series BREQO Output Bus request output The external bus request signal used when an internal bus maste...

Page 44: ...ble upper write enable A strobe signal that writes to external space and indicates that the upper half D15 to D8 of the data bus is enabled The 2CAS type DRAM write enable signal The 2WE type DRAM upper write enable signal LWR Output Low write lower column address strobe lower write enable A strobe signal that writes to external space and indicates that the lower half D7 to D0 of the data bus is e...

Page 45: ...ure output compare match A2 and B2 The TGR2A and TGR2B input capture input or output compare output or PWM output pins TIOCA3 TIOCB3 TIOCC3 TIOCD3 I O Input capture output compare match A3 to D3 The TGR3A to TGR3D input capture input or output compare output or PWM output pins TIOCA4 TIOCB4 I O Input capture output compare match A4 and B4 The TGR4A and TGR4B input capture input or output compare o...

Page 46: ... transmission data receive data Input output pins for the data encoded for the IrDA I2 C bus interface IIC optional SCL0 SCL1 I O I2 C clock input channel 1 0 I2 C clock input output pins These functions have a bus driving function SCL0 s output format is an NMOS open drain SDA0 SDA1 I O I2 C data input output channel 1 0 I2 C clock input output pins These functions have a bus driving function SCL...

Page 47: ...a direction register P7DDR P97 to P90 Input Port 9 An 8 bit input port PA3 to PA0 I O Port A A 4 bit I O port Input or output can be designated for each bit by means of the port A data direction register PADDR PB7 to PB0 I O Port B An 8 bit I O port Input or output can be designated for each bit by means of the port B data direction register PBDDR PC7 to PC0 I O Port C An 8 bit I O port Input or o...

Page 48: ...ister architecture Sixteen 16 bit general registers also usable as sixteen 8 bit registers or eight 32 bit registers Sixty nine basic instructions 8 16 32 bit arithmetic and logic instructions Multiply and divide instructions Powerful bit manipulation instructions Multiply and accumulate instruction Eight addressing modes Register direct Rn Register indirect ERn Register indirect with displacement...

Page 49: ...o power down state by SLEEP instruction CPU clock speed selection 2 1 2 Differences between H8S 2600 CPU and H8S 2000 CPU The differences between the H8S 2600 CPU and the H8S 2000 CPU are as shown below Register configuration The MAC register is supported only by the H8S 2600 CPU Basic instructions The four instructions MAC CLRMAC LDMAC and STMAC are supported only by the H8S 2600 CPU Number of ex...

Page 50: ...een enhanced to make effective use of the 16 Mbyte address space Enhanced instructions Addressing modes of bit manipulation instructions have been enhanced Signed multiply and divide instructions have been added A multiply and accumulate instruction has been added Two bit shift instructions have been added Instructions for saving and restoring multiple registers have been added A test and set inst...

Page 51: ... 2633 Series Normal mode Advanced mode Maximum 64 kbytes program and data areas combined Maximum 16 Mbytes for program and data areas combined Figure 2 1 CPU Operating Modes 1 Normal Mode Not Available in the H8S 2633 Series The exception vector table and stack have the same structure as in the H8 300 CPU Address Space A maximum address space of 64 kbytes can be accessed Extended Registers En The ...

Page 52: ... H 0002 H 0003 H 0004 H 0005 H 0006 H 0007 H 0008 H 0009 H 000A H 000B Power on reset exception vector Manual reset exception vector Exception vector 1 Exception vector 2 Exception vector table Reserved for system use Figure 2 2 Exception Vector Table Normal Mode The memory indirect addressing mode aa 8 employed in the JMP and JSR instructions uses an 8 bit absolute address included in the instruc...

Page 53: ...PC 16 bits SP SP Notes 1 2 3 When EXR is not used it is not stored on the stack SP when EXR is not used Ignored when returning SP 2 Figure 2 3 Stack Structure in Normal Mode 2 Advanced Mode Address Space Linear access is provided to a 16 Mbyte maximum address space architecturally a maximum 16 Mbyte program area and a maximum 4 Gbyte data area with a maximum of 4 Gbytes for program and data areas ...

Page 54: ...ed for system use Reserved Exception vector 1 Reserved Manual reset exception vector H 00000010 H 00000008 H 00000007 Figure 2 4 Exception Vector Table Advanced Mode The memory indirect addressing mode aa 8 employed in the JMP and JSR instructions uses an 8 bit absolute address included in the instruction code to specify a memory operand that contains a branch address In advanced mode the operand ...

Page 55: ...exception handling they are stored as shown in figure 2 5 When EXR is invalid it is not pushed onto the stack For details see section 4 Exception Handling a Subroutine Branch b Exception Handling PC 24 bits EXR 1 Reserved 1 3 CCR PC 24 bits SP SP Notes 1 2 3 When EXR is not used it is not stored on the stack SP when EXR is not used Ignored when returning SP 2 Reserved Figure 2 5 Stack Structure in...

Page 56: ...mum 64 kbyte address space in normal mode and a maximum 16 Mbyte architecturally 4 Gbyte address space in advanced mode b Advanced Mode H 0000 H FFFF H 00000000 H FFFFFFFF H 00FFFFFF a Normal Mode Data area Program area Cannot be used by the H8S 2633 Series Note Not available in the H8S 2633 Series Figure 2 6 Memory Map ...

Page 57: ...ters En Control Registers CR Legend Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition code register Interrupt mask bit User bit or interrupt mask bit SP PC EXR T I2 to I0 CCR I UI Note Cannot be used as an interrupt mask bit in the H8S 2633 Series ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 SP I UI H U N Z V C CCR 7 6 5 4 3 2 1 0 Sign extension 63 32 41 0 31 MAC M...

Page 58: ... to R7 These registers are functionally equivalent providing a maximum sixteen 16 bit registers The E registers E0 to E7 are also referred to as extended registers The R registers divide into 8 bit general registers designated by the letters RH R0H to R7H and RL R0L to R7L These registers are functionally equivalent providing a maximum sixteen 8 bit registers Figure 2 8 illustrates the usage of th...

Page 59: ...Program Counter PC This 24 bit counter indicates the address of the next instruction the CPU will execute The length of all CPU instructions is 2 bytes one word so the least significant PC bit is ignored When an instruction is fetched the least significant PC bit is regarded as 0 2 Extended Control Register EXR This 8 bit register contains the trace bit T and three interrupt mask bits I2 to I0 Bit...

Page 60: ... 5 Interrupt Controller Bit 5 Half Carry Flag H When the ADD B ADDX B SUB B SUBX B CMP B or NEG B instruction is executed this flag is set to 1 if there is a carry or borrow at bit 3 and cleared to 0 otherwise When the ADD W SUB W CMP W or NEG W instruction is executed the H flag is set to 1 if there is a carry or borrow at bit 11 and cleared to 0 otherwise When the ADD L SUB L CMP L or NEG L inst...

Page 61: ...s the results of multiply and accumulate operations It consists of two 32 bit registers denoted MACH and MACL The lower 10 bits of MACH are valid the upper bits are a sign extension 2 4 4 Initial Register Values Reset exception handling loads the CPU s program counter PC from the vector table clears the trace bit in EXR to 0 and sets the interrupt mask bits in CCR and EXR to 1 The other CCR bits a...

Page 62: ...s two digits of 4 bit BCD data 2 5 1 General Register Data Formats Figure 2 10 shows the data formats in general registers 7 6 5 4 3 2 1 0 Don t care 7 0 Don t care 7 6 5 4 3 2 1 0 4 3 7 0 7 0 Don t care Upper Lower LSB MSB LSB Data Type Register Number Data Format 1 bit data 1 bit data 4 bit BCD data 4 bit BCD data Byte data Byte data RnH RnL RnH RnL RnH RnL MSB Don t care Upper Lower 4 3 7 0 Don...

Page 63: ...gister ER General register E General register R General register RH General register RL Most significant bit Least significant bit Legend ERn En Rn RnH RnL MSB LSB 0 MSB LSB 15 Longword data ERn Data Type Register Number Data Format Figure 2 10 General Register Data Formats cont ...

Page 64: ...st significant bit of the address is regarded as 0 so the access starts at the preceding address This also applies to instruction fetches 7 6 5 4 3 2 1 0 7 0 MSB LSB MSB LSB MSB LSB Data Type Data Format 1 bit data Byte data Word data Longword data Address Address L Address L Address 2M Address 2M 1 Address 2N Address 2N 1 Address 2N 2 Address 2N 3 Figure 2 11 Memory Data Formats When ER7 is used ...

Page 65: ...B MAC LDMAC STMAC CLRMAC Logic operations AND OR XOR NOT BWL 4 Shift SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR BWL 8 Bit manipulation BSET BCLR BNOT BTST BLD BILD BST BIST BAND BIAND BOR BIOR BXOR BIXOR B 14 Branch Bcc 2 JMP BSR JSR RTS 5 System control TRAPA RTE SLEEP LDC STC ANDC ORC XORC NOP 9 Block data transfer EEPMOV 1 Notes B byte size W word size L longword size 1 POP W Rn and PUSH W Rn ar...

Page 66: ...ssing Modes Addressing Modes Function Data transfer Arithmetic operations Instruction MOV BWL BWL BWL BWL BWL BWL B BWL BWL POP PUSH WL LDM STM L ADD CMP BWL BWL SUB WL BWL ADDX SUBX B B ADDS SUBS L INC DEC BWL DAA DAS B NEG BWL EXTU EXTS WL TAS B MAC CLRMAC MOVEPE B MOVTPE MULXU BW DIVXU MULXS BW DIVXS LDMAC L STMAC xx Rn ERn d 16 ERn d 32 ERn ERn ERn aa 8 aa 16 aa 24 aa 32 d 8 PC d 16 PC aa 8 ...

Page 67: ...nch Instruction AND OR BWL BWL XOR ANDC B ORC XORC Bcc BSR JMP JSR l RTS TRAPA RTE SLEEP LDC B B W W W W W W STC B W W W W W W NOT BWL BWL B B B B B NOP BW Legend B Byte W Word L Longword xx Rn ERn d 16 ERn d 32 ERn ERn ERn aa 8 aa 16 aa 24 aa 32 d 8 PC d 16 PC aa 8 Note Not available in the H8S 2633 Series ...

Page 68: ...Ad Destination operand EAs Source operand EXR Extended control register CCR Condition code register N N negative flag in CCR Z Z zero flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT logical complement 8 16 24 32 8 16 2...

Page 69: ... more general registers onto the stack Arithmetic operations ADD SUB B W L Rd Rs Rd Rd IMM Rd Performs addition or subtraction on data in two general registers or on immediate data and data in a general register Immediate byte data cannot be subtracted from byte data in a general register Use the SUBX or ADD instruction ADDX SUBX B Rd Rs C Rd Rd IMM C Rd Performs addition or subtraction with carry...

Page 70: ...Compares data in a general register with data in another general register or with immediate data and sets CCR bits according to the result NEG B W L 0 Rd Rd Takes the two s complement arithmetic complement of data in a general register EXTU W L Rd zero extension Rd Extends the lower 8 bits of a 16 bit register to word size or the lower 16 bits of a 32 bit register to longword size by padding with ...

Page 71: ...ral register contents 1 bit or 2 bit shift is possible SHLL SHLR B W L Rd shift Rd Performs a logical shift on general register contents 1 bit or 2 bit shift is possible ROTL ROTR B W L Rd rotate Rd Rotates general register contents 1 bit or 2 bit rotation is possible ROTXL ROTXR B W L Rd rotate Rd Rotates general register contents through the carry flag 1 bit or 2 bit rotation is possible Bit man...

Page 72: ...ral register or memory operand and stores the result in the carry flag C bit No of EAd C ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag The bit number is specified by 3 bit immediate data BXOR BIXOR B B C bit No of EAd C Exclusive ORs the carry flag with a specified bit in a general register or memory operand a...

Page 73: ...ition BRA BT Always true Always BRN BF Never false Never BHI High C Z 0 BLS Low or same C Z 1 BCC BHS Carry clear high or same C 0 BCS BLO Carry set low C 1 BNE Not equal Z 0 BEQ Equal Z 1 BVC Overflow clear V 0 BVS Overflow set V 1 BPL Plus N 0 BMI Minus N 1 BGE Greater or equal N V 0 BLT Less than N V 1 BGT Greater than Z N V 0 BLE Less or equal Z N V 1 JMP Branches unconditionally to a specifie...

Page 74: ...CR EXR IMM EXR Logically ORs the CCR or EXR contents with immediate data XORC B CCR IMM CCR EXR IMM EXR Logically exclusive ORs the CCR or EXR contents with immediate data NOP PC 2 PC Only increments the program counter Block data transfer instruction EEPMOV B EEPMOV W if R4L 0 then Repeat ER5 ER6 R4L 1 R4L Until R4L 0 else next if R4 0 then Repeat ER5 ER6 R4 1 R4 Until R4 0 else next Transfers a ...

Page 75: ...ation to be carried out on the operand The operation field always includes the first four bits of the instruction Some instructions have two operation fields 2 Register Field Specifies a general register Address registers are specified by 3 bits data registers by 3 bits or 4 bits Some instructions have two register fields Some have no register field 3 Effective Address Extension Eight 16 or 32 bit...

Page 76: ...V B d 16 Rn Rm etc 1 Operation field only 2 Operation field and register fields 3 Operation field register fields and effective address extension rn rm op EA disp 4 Operation field effective address extension and condition field op cc EA disp BRA d 16 etc Figure 2 12 Instruction Formats Examples ...

Page 77: ...rect with pre decrement ERn ERn 5 Absolute address aa 8 aa 16 aa 24 aa 32 6 Immediate xx 8 xx 16 xx 32 7 Program counter relative d 8 PC d 16 PC 8 Memory indirect aa 8 1 Register Direct Rn The register field of the instruction specifies an 8 16 or 32 bit general register containing the operand R0H to R7H and R0L to R7L can be specified as 8 bit registers R0 to R7 and E0 to E7 can be specified as 1...

Page 78: ...n For word or longword transfer instruction the register value should be even 5 Absolute Address aa 8 aa 16 aa 24 or aa 32 The instruction code contains the absolute address of a memory operand The absolute address may be 8 bits long aa 8 16 bits long aa 16 24 bits long aa 24 or 32 bits long aa 32 To access data the absolute address should be 8 bits aa 8 16 bits aa 16 or 32 bits aa 32 long For an ...

Page 79: ...added is the address of the first byte of the next instruction so the possible branching range is 126 to 128 bytes 63 to 64 words or 32766 to 32768 bytes 16383 to 16384 words from the branch instruction The resulting value should be an even number 8 Memory Indirect aa 8 This mode can be used by the JMP and JSR instructions The instruction code contains an 8 bit absolute address specifying a memory...

Page 80: ...nch address the least significant bit is regarded as 0 causing data to be accessed or instruction code to be fetched at the address preceding the specified address For further information see section 2 5 2 Memory Data Formats 2 7 2 Effective Address Calculation Table 2 6 indicates how effective addresses are calculated in each addressing mode In normal mode the upper 8 bits of the effective addres...

Page 81: ...eral register contents Register indirect ERn 2 Register indirect with displacement d 16 ERn or d 32 ERn 3 Register indirect with pre decrement ERn 4 General register contents General register contents Sign extension disp General register contents 1 2 or 4 General register contents 1 2 or 4 Byte Word Longword 1 2 4 Operand Size Value added 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 op r r op op r...

Page 82: ...8 7 Operand is immediate data No Addressing Mode and Instruction Format Effective Address Calculation Effective Address EA aa 24 31 0 16 15 31 0 24 23 31 0 op abs op abs abs op op abs op IMM H FFFF Don t care 24 23 Don t care 24 23 Don t care 24 23 Don t care Sign extension ...

Page 83: ...Instruction Format Effective Address Calculation Effective Address EA 23 23 31 8 7 0 15 0 31 8 7 0 disp H 000000 abs H 000000 31 0 24 23 31 0 16 15 31 0 24 23 op disp op abs op abs Sign extension PC contents abs Memory contents Memory contents H 00 Don t care 24 23 Don t care Don t care Note Not available in the H8S 2633 Series ...

Page 84: ...ransient state in which the CPU changes the normal processing flow in response to a reset interrupt or trap instruction Program execution state The CPU executes program instructions in sequence Bus released state The external bus has been released in response to a bus request signal from a bus master other than the CPU Power down state CPU operation is stopped to conserve power Sleep mode Software...

Page 85: ...te when the watchdog timer overflows From any state a transition to hardware standby mode occurs when STBY goes low Apart from these states there are also the watch mode subactive mode and the subsleep mode See Chapter 24 Power Down States E n d o f e x c e p t i o n h a n d l i n g Manual reset state 1 MRES High Reset state 1 Figure 2 15 State Transitions 2 8 2 Reset State The CPU enters the rese...

Page 86: ... clock Exception handling starts immediately after a low to high transition at the RES pin or when the watchdog timer overflows Trace End of instruction execution or end of exception handling sequence 1 When the trace T bit is set to 1 the trace starts at the end of the current instruction or current exception handling sequence Interrupt End of instruction execution or end of exception handling se...

Page 87: ...trace exception handling starts at the end of each instruction At the end of a trace exception handling sequence the T bit of EXR is cleared to 0 and trace mode is cleared Interrupt masks are not affected The T bit saved on the stack retains its value of 1 and when the RTE instruction is executed to return from the trace exception handling routine trace mode is entered again Trace exception handli...

Page 88: ...P EXR Reserved 1 a Interrupt control mode 0 b Interrupt control mode 2 CCR CCR 1 PC 16 bits SP CCR CCR 1 PC 16 bits SP EXR Reserved 1 Normal mode 2 Advanced mode Notes 1 Ignored when returning 2 Not available in the H8S 2633 Series Figure 2 16 Stack Structure after Exception Handling Examples ...

Page 89: ...ividual modules other than the CPU Subactive mode subsleep mode and watch mode are power down states using subclock input For details refer to section 24 Power Down State 1 Sleep Mode A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit SSBY in the standby control register SBYCR is cleared to 0 In sleep mode CPU operations stop immediately after ex...

Page 90: ...on chip supporting modules and the external address space 2 9 2 On Chip Memory ROM RAM On chip memory is accessed in one state The data bus is 16 bits wide permitting both byte and word transfer instruction Figure 2 17 shows the on chip memory access cycle Figure 2 18 shows the pin states Internal address bus Internal read signal Internal data bus Internal write signal Internal data bus ø Bus cycl...

Page 91: ...64 Bus cycle T1 Unchanged Address bus AS RD HWR LWR Data bus ø High High High High impedance state Figure 2 18 Pin States during On Chip Memory Access ...

Page 92: ...articular internal I O register being accessed Figure 2 19 shows the access timing for the on chip supporting modules Figure 2 20 shows the pin states Bus cycle T1 T2 Address Read data Write data Internal read signal Internal data bus Internal write signal Internal data bus Read access Write access Internal address bus ø Figure 2 19 On Chip Supporting Module Access Cycle ...

Page 93: ...us width in a two state or three state bus cycle In three state access wait states can be inserted For further details refer to section 7 Bus Controller 2 10 Usage Note 2 10 1 TAS Instruction Only register ER0 ER1 ER4 or ER5 should be used when using the TAS instruction The TAS instruction is not generated by the Hitachi H8S and H8 300 series C C compilers If the TAS instruction is used as a user ...

Page 94: ...bits 5 1 8 bits 16 bits 6 1 0 On chip ROM enabled expanded mode Enabled 8 bits 16 bits 7 1 Single chip mode Note Not available in the H8S 2633 Series The CPU s architecture allows for 4 Gbytes of address space but the H8S 2633 Series actually accesses a maximum of 16 Mbytes Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices The external expansion...

Page 95: ...ster PFCR R W H 0D H 00 H FDEB Note Lower 16 bits of the address 3 2 Register Descriptions 3 2 1 Mode Control Register MDCR 7 1 R W 6 0 5 0 4 0 3 0 0 MDS0 R 2 MDS2 R 1 MDS1 R Note Determined by pins MD2 to MD0 Bit Initial value R W MDCR is an 8 bit register that indicates the current operating mode of the H8S 2633 Series Bit 7 Reserved Only 1 should be written to this bit Bits 6 to 3 Reserved Thes...

Page 96: ... initialized SYSCR is not initialized in software standby mode Bit 7 MAC Saturation MACS Selects either saturating or non saturating calculation for the MAC instruction Bit 7 MACS Description 0 Non saturating calculation for MAC instruction Initial value 1 Saturating calculation for MAC instruction Bit 6 Reserved This bit always read as 0 and cannot be modified Bits 5 and 4 Interrupt Control Mode ...

Page 97: ...Disenables manual reset Possible to use P74 TM02 MRES pin as P74 TM02 input pin Initial value 1 Enables manual reset Possible to use P74 TM02 MRES pin as MRES input pin Table 3 3 Relationship Between Power On Reset and Manual Reset Pin RES MRES Reset Type 0 Power on reset Initial state 1 0 Manual reset 1 1 Operation state Don t care Bit 1 Reserved This bit always read as 0 and cannot be modified B...

Page 98: ... is initialized by H 0D H 00 by a power on reset or a hardware standby mode The immediately previous state is maintained in manual reset or software standby mode Bit 7 CS0 CS7 Select CSS07 Selects the CS output content for PG4 pin In modes 4 to 6 the selected CS is output by setting the corresponding DDR to 1 Bit 7 CSS07 Description 0 Select CS0 Initial value 1 Select CS7 Bit 6 CS3 CS6 Select CSS3...

Page 99: ...the LCAS signal output pin Bit 4 LCASS Description 0 Outputs LCAS signal from PF2 Initial Value 1 Outputs LCAS signal from PF6 Bits 3 to 0 Address Output Enable 3 to 0 AE3 AE0 These bits select enabling or disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM When a pin is enabled for address output the address is output regardless of the corresponding DDR setting When...

Page 100: ...t disabled 1 0 0 0 A8 A15 address output enabled A16 A23 address output disabled 1 A8 A16 address output enabled A17 A23 address output disabled 1 0 A8 A17 address output enabled A18 A23 address output disabled 1 A8 A18 address output enabled A19 A23 address output disabled 1 0 0 A8 A19 address output enabled A20 A23 address output disabled 1 A8 A20 address output enabled A21 A23 address output di...

Page 101: ...8 bit access to all areas However note that if 16 bit access is designated by the bus controller for any area the bus mode switches to 16 bits and port E becomes a data bus 3 3 3 Mode 6 The CPU can access a 16 Mbyte address space in advanced mode The on chip ROM is enabled Ports 1 A B and C function as input port pins immediately after a reset Address output can be performed by setting the corresp...

Page 102: ...Port C A A P A P Port D D D D P Port E P D P D P D P Port F PF7 P C P C P C P C PF6 to PF4 C C C P PF3 P C P C P C PF2 to PF0 P C P C P C Legend P I O port A Address bus output D Data bus I O C Control signals clock I O After reset 3 5 Address Map in Each Operating Mode A address map of the H8S 2633 is shown in figure 3 1 and a address map of the H8S 2632 in figure 3 2 The address space is 16 kbyt...

Page 103: ...nternal I O registers Notes H FFFFFF H FFFF40 H FFFF60 H FFFFC0 H FFB000 H FFB000 H FFEFC0 H FFF800 H FFFF40 H FFFF60 H FFFFC0 H FFFF60 H FFFFC0 On chip RAM 1 On chip RAM External area H FFFFFF H FFFFFF H FFF800 H FFFF3F 1 External addresses can be accessed by clearing th RAME bit in SYSCR to 0 2 Area H FFF800 to H FFFDAB is reserved and must not be accessed Modes 4 and 5 advanced expanded modes w...

Page 104: ...Internal I O registers 2 External area Internal I O registers On chip RAM 1 External area Internal I O registers On chip ROM External address space On chip ROM On chip RAM Internal I O registers H FFFFFF H FFFF40 H FFFF60 H FFFFC0 H FFC000 H FFC000 H FFEFC0 H FFF800 H FFFF40 H FFFF60 H FFFFC0 H FFFF60 H FFFFC0 On chip RAM 1 On chip RAM External area H FFFFFF H FFFFFF H FFF800 H FFFF3F Reserved are...

Page 105: ...O registers On chip RAM 1 External area Internal I O registers On chip ROM External address space On chip ROM On chip RAM Internal I O registers 2 Internal I O registers H FFFFFF H FFFF40 H FFFF60 H FFFFC0 H FFD000 H FFD000 H FFEFC0 H FFF800 H FFFF40 H FFFF60 H FFFFC0 H FFFF60 H FFFFC0 On chip RAM 1 On chip RAM External area Internal I O registers 2 H FFFFFF H FFFFFF H FFF800 H FFFF3F Reserved are...

Page 106: ...RES pin or MRES pin or when the watchdog overflows The CPU enters the power on reset state when the RES pin is low and the manual reset state when the MRES pin is low Trace 1 Starts when execution of the current instruction or exception handling ends if the trace T bit is set to 1 Direct transition Starts when a direct transition occurs due to execution of a SLEEP instruction Interrupt Starts when...

Page 107: ...s generated and program execution starts from that address For a reset exception steps 2 and 3 above are carried out 4 1 3 Exception Vector Table The exception sources are classified as shown in figure 4 1 Different vector addresses are assigned to different exception sources Table 4 2 lists the exception sources and their vector addresses Exception sources Reset Trace Interrupts Trap instruction ...

Page 108: ... 0028 to H 002B 11 H 002C to H 002F Reserved for system use 12 H 0030 to H 0033 13 H 0034 to H 0037 14 H 0038 to H 003B 15 H 003C to H 003F External interrupt IRQ0 16 H 0040 to H 0043 IRQ1 17 H 0044 to H 0047 IRQ2 18 H 0048 to H 004B IRQ3 19 H 004C to H 004F IRQ4 20 H 0050 to H 0053 IRQ5 21 H 0054 to H 0057 IRQ6 22 H 0058 to H 005B IRQ7 23 H 005C to H 005F Internal interrupt 2 24 127 H 0060 to H 0...

Page 109: ...are two types of reset power on reset and manual reset Table 4 3 shows the types of reset When turning power on do so as a power on reset Both power on reset and manual reset initialize the internal state of the CPU In a power on reset all of the registers of the built in vicinity modules are initialized while in a manual reset the registers of the built in vicinity models except for bus controlle...

Page 110: ...for at least 20 ms at power up To reset during operation hold the RES pin or the MRES pin low for at least 20 states When the RES pin or the MRES pin goes high after being held low for the necessary time this LSI starts reset exception handling as follows 1 The internal state of the CPU and the registers of the on chip supporting modules are initialized the T bit is cleared to 0 in EXR and the I b...

Page 111: ...ction 1 3 Reset exception handling vector address when power on reset 1 H 000000 3 H 000002 when manual reset 1 H 000004 3 H 000006 2 4 Start address contents of reset exception handling vector address 5 Start address 5 2 4 6 First program instruction Note 3 program wait states are inserted Figure 4 2 Reset Sequence Modes 4 and 5 ...

Page 112: ...r SP is initialized the PC and CCR will not be saved correctly leading to a program crash To prevent this all interrupt requests including NMI are disabled immediately after a reset Since the first instruction of a program is always executed immediately after the reset state ends make sure that this instruction initializes the stack pointer example MOV L xx 32 SP 4 2 5 State of On Chip Supporting ...

Page 113: ...rrupt masking Table 4 4 shows the state of CCR and EXR after execution of trace exception handling Interrupts are accepted even within the trace exception handling routine The T bit saved on the stack retains its value of 1 and when control is returned from the trace exception handling routine by the RTE instruction trace mode resumes Trace exception handling is not carried out after execution of ...

Page 114: ...rity interrupt Interrupts are controlled by the interrupt controller The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority mask levels to enable multiplexed interrupt control For details of interrupts see section 5 Interrupt Controller Interrupts External interrupts Internal interrupts NMI 1 IRQ7 to IRQ0 8 WDT 1 2 Refresh timer 2 1 TPU ...

Page 115: ...etches a start address from a vector table entry corresponding to a vector number from 0 to 3 as specified in the instruction code Table 4 5 shows the status of CCR and EXR after execution of trap instruction exception handling Table 4 5 Status of CCR and EXR after Trap Instruction Exception Handling CCR EXR Interrupt Control Mode I UI I2 to I0 T 0 1 2 1 0 Legend 1 Set to 1 0 Cleared to 0 Retains ...

Page 116: ...R PC 16 bits Reserved EXR a Interrupt control mode 0 b Interrupt control mode 2 Note Ignored on return Figure 4 5 1 Stack Status after Exception Handling Normal Modes Not Available in the H8S 2633 Series SP SP CCR PC 24bits CCR PC 24bits Reserved EXR a Interrupt control mode 0 b Interrupt control mode 2 Note Ignored on return Figure 4 5 2 Stack Status after Exception Handling Advanced Modes ...

Page 117: ...lowing instructions to restore registers POP W Rn or MOV W SP Rn POP L ERn or MOV L SP ERn Setting SP to an odd value may lead to a malfunction Figure 4 6 shows an example of what happens when the SP value is odd SP Legend Note This diagram illustrates an example in which the interrupt control mode is 0 in advanced mode SP SP CCR PC R1L PC H FFFEFA H FFFEFB H FFFEFC H FFFEFD H FFFEFF MOV B R1L ER7...

Page 118: ...riority levels can be set for each module for all interrupts except NMI NMI is assigned the highest priority level of 8 and can be accepted at all times Independent vector addresses All interrupt sources are assigned independent vector addresses making it unnecessary for the source to be identified in the interrupt handling routine Nine external interrupts NMI is the highest priority interrupt and...

Page 119: ...INTM1 INTM0 NMIEG NMI input unit IRQ input unit ISR ISCR IER IPR Interrupt controller Priority determination Interrupt request Vector number I I2 to I0 CCR EXR CPU ISCR IER ISR IPR SYSCR IRQ sense control register IRQ enable register IRQ status register Interrupt priority register System control register Legend Figure 5 1 Block Diagram of Interrupt Controller ...

Page 120: ...sense control register L ISCRL R W H 00 H FE13 IRQ enable register IER R W H 00 H FE14 IRQ status register ISR R W 2 H 00 H FE15 Interrupt priority register A IPRA R W H 77 H FEC0 Interrupt priority register B IPRB R W H 77 H FEC1 Interrupt priority register C IPRC R W H 77 H FEC2 Interrupt priority register D IPRD R W H 77 H FEC3 Interrupt priority register E IPRE R W H 77 H FEC4 Interrupt priori...

Page 121: ...al reset and in hardware standby mode SYSCR is not initialized in software standby mode Bits 5 and 4 Interrupt Control Mode 1 and 0 INTM1 INTM0 These bits select one of two interrupt control modes for the interrupt controller Bit 5 Bit 4 Interrupt INTM1 INTM0 Control Mode Description 0 0 0 Interrupts are controlled by I bit Initial value 1 Setting prohibited 1 0 2 Interrupts are controlled by bits...

Page 122: ... NMI The IPR registers are initialized to H 77 by a reset and in hardware standby mode Bits 7 and 3 Reserved These bits are always read as 0 and cannot be modified Table 5 3 Correspondence between Interrupt Sources and IPR Settings Bits Register 6 to 4 2 to 0 IPRA IRQ0 IRQ1 IPRB IRQ2 IRQ3 IRQ4 IRQ5 IPRC IRQ6 IRQ7 DTC IPRD Watchdog timer 0 Refresh timer IPRE PC break A D converter watchdog timer 1 ...

Page 123: ...o I0 in the extend register EXR in the CPU and if the priority level of the interrupt is higher than the set mask level an interrupt request is issued to the CPU 5 2 3 IRQ Enable Register IER 7 IRQ7E 0 R W 6 IRQ6E 0 R W 5 IRQ5E 0 R W 4 IRQ4E 0 R W 3 IRQ3E 0 R W 0 IRQ0E 0 R W 2 IRQ2E 0 R W 1 IRQ1E 0 R W Bit Initial value R W IER is an 8 bit readable writable register that controls enabling and disa...

Page 124: ...r both edge detection or level sensing for the input at pins IRQ7 to IRQ0 The ISCR registers are initialized to H 0000 by a reset and in hardware standby mode They are not initialized in software standby mode Bits 15 to 0 IRQ7 Sense Control A and B IRQ7SCA IRQ7SCB to IRQ0 Sense Control A and B IRQ0SCA IRQ0SCB Bits 15 to 0 IRQ7SCB to IRQ0SCB IRQ7SCA to IRQ0SCA Description 0 0 Interrupt request gene...

Page 125: ...leared by reading IRQnF flag when IRQnF 1 then writing 0 to IRQnF flag When interrupt exception handling is executed when low level detection is set IRQnSCB IRQnSCA 0 and IRQn input is high When IRQn interrupt exception handling is executed when falling rising or both edge detection is set IRQnSCB 1 or IRQnSCA 1 When the DTC is activated by an IRQn interrupt and the DISEL bit in MRB of the DTC is ...

Page 126: ...mber for NMI interrupt exception handling is 7 IRQ7 to IRQ0 Interrupts Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0 Interrupts IRQ5 to IRQ0 have the following features Using ISCR it is possible to select whether an interrupt is generated by a low level falling edge rising edge or both edges at pins IRQ7 to IRQ0 Enabling or disabling of interrupt requests IRQ7 to IR...

Page 127: ...enable bits that select enabling or disabling of these interrupts If both of these are set to 1 for a particular interrupt source an interrupt request is issued to the interrupt controller The interrupt priority level can be set by means of IPR The DMAC and DTC can be activated by a TPU 8 bit timer SCI or other interrupt request When the DMAC and DTC are activated by an interrupt the interrupt con...

Page 128: ...vation interrupt end DTC 24 H 0060 IPRC2 to 0 WOVI0 interval timer Watchdog timer 0 25 H 0064 IPRD6 to 4 CMI Refresh timer 26 H 0068 IPRD2 to 0 PC break PC break 27 H 006C IPRE6 to 4 ADI A D conversion end A D 28 H 0070 IPRE2 to 0 WOVI1 interval timer Watchdog timer 1 29 H 0074 Reserved 30 31 H 0078 H 007C TGI0A TGR0A input capture compare match TGI0B TGR0B input capture compare match TGI0C TGR0C ...

Page 129: ...G6 to 4 TGI3A TGR3A input capture compare match TGI3B TGR3B input capture compare match TGI3C TGR3C input capture compare match TGI3D TGR3D input capture compare match TCI3V overflow 3 TPU channel 3 48 49 50 51 52 H 00C0 H 00C4 H 00C8 H 00CC H 00D0 IPRG2 to 0 Reserved 53 54 55 H 00D4 H 00D8 H 00DC TGI4A TGR4A input capture compare match TGI4B TGR4B input capture compare match TCI4V overflow 4 TCI4...

Page 130: ...END1A channel 1 channel 1A transfer end DEND1B channel 1B transfer end DMAC 72 73 74 75 H 0120 H 0124 H 0128 H 012C IPRJ6 to 4 Reserved 76 77 78 79 H 0130 H 0134 H 0138 H 013C ERI0 receive error 0 RXI0 reception completed 0 TXI0 transmit data empty 0 TEI0 transmission end 0 SCI channel 0 80 81 82 83 H 0140 H 0144 H 0148 H 014C IPRJ2 to 0 ERI1 receive error 1 RXI1 reception completed 1 TXI1 transmi...

Page 131: ...mission reception completed Reserved IIC channel 1 optional 102 103 H 0198 H 019C Reserved 104 105 106 107 H 01A0 H 01A4 H 01A8 H 01AC IPRM6 to 4 Reserved 108 109 110 111 H 01B0 H 01B4 H 01B8 H 01BC IPRM2 to 0 Reserved 112 113 114 115 H 01C0 H 01C4 H 01C8 H 01CC IPRN6 to 4 Reserved 116 117 118 119 H 01D0 H 01D4 H 01D8 H 01DC IPRN2 to 0 ERI3 reception error 3 RXI3 reception completed 3 TXI3 transmi...

Page 132: ... are set to 1 are controlled by the interrupt controller Table 5 5 shows the interrupt control modes The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR the priorities set in IPR and the masking state indicated by the I and UI bits in the CPU s CCR and bits I2 to I0 in EXR Table 5 5 Interrupt Control Modes Interrupt S...

Page 133: ... 0 I Figure 5 4 Block Diagram of Interrupt Control Operation 1 Interrupt Acceptance Control In interrupt control mode 0 interrupt acceptance is controlled by the I bit in CCR Table 5 6 shows the interrupts selected in each interrupt control mode Table 5 6 Interrupts Selected in Each Interrupt Control Mode 1 Interrupt Mask Bits Interrupt Control Mode I Selected Interrupts 0 0 All interrupts 1 NMI i...

Page 134: ...ctor number is generated If the same value is set for IPR acceptance of multiple interrupts is enabled and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated Interrupt sources with a lower priority than the accepted interrupt source are held pending Table 5 8 shows operations and control signal functions i...

Page 135: ... and other interrupt requests are held pending 3 Interrupt requests are sent to the interrupt controller the highest ranked interrupt according to the priority system is accepted and other interrupt requests are held pending 4 When an interrupt request is accepted interrupt exception handling starts after execution of the current instruction has been completed 5 The PC and CCR are saved to the sta...

Page 136: ...ated NMI IRQ0 IRQ1 TEI4 I 0 Save PC and CCR I 1 Read vector address Branch to interrupt handling routine Yes No Yes Yes Yes No No No Yes Yes No Hold pending Figure 5 5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 ...

Page 137: ...le 5 4 is selected 3 Next the priority of the selected interrupt request is compared with the interrupt mask level set in EXR An interrupt request with a priority no higher than the mask level set at that time is held pending and only an interrupt request with a priority higher than the interrupt mask level is accepted 4 When an interrupt request is accepted interrupt exception handling starts aft...

Page 138: ...ask level 6 or below Save PC CCR and EXR Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Hold pending Level 1 interrupt Mask level 0 Yes Yes No Yes Yes Yes No Yes Yes No No No No No No Figure 5 6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 ...

Page 139: ...tance Interrupt level determination Wait for end of instruction Interrupt request signal Internal address bus Internal read signal Internal write signal Internal data us ø 3 1 2 4 3 5 7 Instruction prefetch address Not executed This is the contents of the saved PC the return address Instruction code Not executed Instruction prefetch address Not executed SP 2 SP 4 Saved PC and saved CCR Vector addr...

Page 140: ...anced Mode No Execution Status INTM1 0 INTM1 1 INTM1 0 INTM1 1 1 Interrupt priority determination 1 3 3 3 3 2 Number of wait states until executing instruction ends 2 1 to 19 2 SI 1 to 19 2 SI 1 to 19 2 SI 1 to 19 2 SI 3 PC CCR EXR stack save 2 SK 3 SK 2 SK 3 SK 4 Vector fetch SI SI 2 SI 2 SI 5 Instruction fetch 3 2 SI 2 SI 2 SI 2 SI 6 Internal processing 4 2 2 2 2 Total using on chip memory 11 to...

Page 141: ...ecution of the instruction In other words when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV if an interrupt is generated during execution of the instruction the interrupt concerned will still be enabled on completion of the instruction and so interrupt exception handling for that interrupt will be executed on completion of the instruction However if there is an int...

Page 142: ...hat disable interrupts are LDC ANDC ORC and XORC After any of these instructions is executed all interrupts including NMI are disabled and the next instruction is always executed When the I bit is set by one of these instructions the new value becomes valid two states after execution of the instruction ends 5 5 3 Times when Interrupts are Disabled There are times when interrupt acceptance is disab...

Page 143: ...he address of the next instruction Therefore if an interrupt is generated during execution of an EEPMOV W instruction the following coding should be used L1 EEPMOV W MOV W R4 R4 BNE L1 5 6 DTC and DMAC Activation by Interrupt 5 6 1 Overview The DTC and DMAC can be activated by an interrupt In this case the following options are available Interrupt request to CPU Activation request to DTC Activatio...

Page 144: ...annel of DMAC are selected by DTF3 to DTF0 bits of DMACR The DTA bit of DMABCR can be used to select whether the selected activation factors are managed by DMAC By setting the DTA bit to 1 the interrupt factor which were the activation factor for that DMAC do not act as the DTC activation factor or the CPU interrupt factor Interrupt factors other than the interrupts managed by the DMAC are selecte...

Page 145: ... and bus priorities Table 5 11 shows the interrupt factor clear control and selection of interrupt factors by specification of the DTA bit of DMAC s DMABCR DTC s DTCERA to DTCERF DTCERI s DTCE bits and the DISEL bit of DTC s MRB Table 5 11 Interrupt Source Selection and Clearing Control Settings DMAC DTC Interrupt Source Selection Clearing Control DTA DTCE DISEL DMAC DTC CPU 0 0 X 1 0 X 1 1 X X Le...

Page 146: ...break channels A and B The following can be set as break compare conditions 24 address bits Bit masking possible Bus cycle Instruction fetch Data access data read data write data read write Bus master Either CPU or CPU DTC can be selected The timing of PC break exception handling after the occurrence of a break condition is as follows Immediately before execution of the instruction fetched at the ...

Page 147: ... break controller Output control Mask control Output control Match signal PC break interrupt Match signal Mask control BARA BCRA BARB BCRB Comparator Control logic Comparator Control logic Internal address Access status Figure 6 1 Block Diagram of PC Break Controller ...

Page 148: ...n be written for flag clearing 6 2 Register Descriptions 6 2 1 Break Address Register A BARA Bit Initial value R W 31 Unde fined 24 Unde fined R W BAA 23 23 0 R W BAA 22 22 0 R W BAA 21 21 0 R W BAA 20 20 0 R W BAA 19 19 0 R W BAA 18 18 0 R W BAA 17 17 0 R W BAA 16 16 0 R W 0 BAA 7 7 R W 0 BAA 6 6 R W 0 BAA 5 5 R W 0 BAA 4 4 R W 0 BAA 3 3 R W 0 BAA 2 2 R W 0 BAA 1 1 R W 0 BAA 0 0 BARA is a 32 bit ...

Page 149: ... specifies whether the break condition is applied to an instruction fetch or a data access It also contains a condition match flag BCRA is initialized to H 00 by a power on reset and in hardware standby mode Bit 7 Condition Match Flag A CMFA Set to 1 when a break condition set for channel A is satisfied This flag is not cleared to 0 Bit 7 CMFA Description 0 Clearing condition When 0 is written to ...

Page 150: ...asked and not included in break conditions 1 0 BAA11 0 lower 12 bits are masked and not included in break conditions 1 BAA15 0 lower 16 bits are masked and not included in break conditions Bits 2 and 1 Break Condition Select A CSELA1 CSELA0 These bits selection an instruction fetch data read data write or data read write cycle as the channel A break condition Bit 2 Bit 1 CSELA1 CSELA0 Description ...

Page 151: ... When the MSTPC4 bit is set to 1 PC break controller operation is stopped at the end of the bus cycle and module stop mode is entered Register read write accesses are not possible in module stop mode For details see section 24 5 Module Stop Mode MSTPCRC is initialized to H FF by a power on reset and in hardware standby mode It is not initialized by a manual reset and in software standby mode Bit 4...

Page 152: ...able break interrupts 2 Satisfaction of break condition When the instruction at the set address is fetched a PC break request is generated immediately before execution of the fetched instruction and the condition match flag CMFA is set 3 Interrupt handling After priority determination by the interrupt controller PC break interrupt exception handling is started 6 3 2 PC Break Interrupt Due to Data ...

Page 153: ...controller 6 3 4 Operation in Transitions to Power Down Modes The operation when a PC break interrupt is set for an instruction fetch at the address after a SLEEP instruction is shown below 1 When the SLEEP instruction causes a transition from high speed medium speed mode to sleep mode or from subactive mode to subsleep mode After execution of the SLEEP instruction a transition is not made to slee...

Page 154: ...lock system clock oscillation settling time SLEEP instruction execution Transition to respective mode Direct transition exception handling PC break exception handling Execution of instruction after sleep instruction PC break exception handling Execution of instruction after sleep instruction A B C D SLEEP instruction execution Figure 6 2 Operation in Power Down Mode Transitions 6 3 5 PC Break Oper...

Page 155: ...later than in normal operation 3 When break interruption by instruction fetch is set and a break interrupt is generated if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below and that address indicates on chip ROM or RAM and that address is used for data access the instruction will be one state later than in normal operation ERn d 16 ERn ...

Page 156: ...ince interrupts including NMI are disabled for a 3 state period in the case of LDC ANDC ORC and XORC the next instruction is always executed For details see section 5 Interrupt Controller 3 When a PC break is set for an instruction fetch at the address following a Bcc instruction A PC break interrupt is generated if the instruction at the next address is executed in accordance with the branch cond...

Page 157: ... in area units Manages the external space as 8 areas of 2 Mbytes Bus specifications can be set independently for each area DRAM Burst ROM interface can be set Basic bus interface Chip selects CS0 to CS7 can be output for areas 0 to 7 8 bit access or 16 bit access can be selected for each area 2 state access or 3 state access can be selected for each area Program wait states can be inserted for eac...

Page 158: ... external read cycle Write buffer functions External write cycle and internal access can be executed in parallel DMAC single address mode and internal access can be executed in parallel Bus arbitration function Includes a bus arbiter that arbitrates bus mastership among the CPU DMAC and DTC Other features Refresh counter refresh timer can be used as an interval timer External bus release function ...

Page 159: ...register H WCRL Wait control register L MCR DRAMCR RTCNT RTCOR Memory control register DRAM control register Refresh timer counter Refresh time constand register BREQ BACK BREQO Internal control signals Wait controller WCRH WCRL DRAM controller External DRAM control signal MCR DRAMCR RTCNT RTCOR Bus mode signal Bus arbiter CPU bus request signal DTC bus request signal DMAC bus request signal CPU b...

Page 160: ...ress strobe signal for DRAM When areas 2 to 5 are contiguous DRAM space this is the row address strobe signal for DRAM Chip select 3 row address strobe 3 CS3 OE Output Strobe signal showing selection of area 3 When area 3 is allocated to DRAM space this is the row address strobe signal for DRAM When only area 2 is allocated to DRAM space or when areas 2 to 5 are contiguous DRAM space this is outpu...

Page 161: ...me Abbreviation R W Power On Reset Manual Reset Address 1 Bus width control register ABWCR R W H FF H 00 2 Retained H FED0 Access state control register ASTCR R W H FF Retained H FED1 Wait control register H WCRH R W H FF Retained H FED2 Wait control register L WCRL R W H FF Retained H FED3 Bus control register H BCRH R W H D0 Retained H FED4 Bus control register L BCRL R W H 08 Retained H FED5 Pi...

Page 162: ... space The bus width for on chip memory and internal I O registers is fixed regardless of the settings in ABWCR In normal mode the settings of bits ABW7 to ABW1 have no effect on operation After a power on reset and in hardware standby mode ABWCR is initialized to H FF in modes 5 to 7 and to H 00 in mode 4 It is not initialized by a manual reset or in software standby mode Bits 7 to 0 Area 7 to 0 ...

Page 163: ...l mode the settings of bits AST7 to AST1 have no effect on operation ASTCR is initialized to H FF by a power on reset and in hardware standby mode It is not initialized by a manual reset or in software standby mode Bits 7 to 0 Area 7 to 0 Access State Control AST7 to AST0 These bits select whether the corresponding area is to be designated as a 2 state access space or a 3 state access space Wait s...

Page 164: ...e the AST7 bit in ASTCR is set to 1 Bit 7 Bit 6 W71 W70 Description 0 0 Program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 1 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed Initial value Bits 5 and 4 Area 6 Wait Control...

Page 165: ...ea 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed Initial value Bits 1 and 0 Area 4 Wait Control 1 and 0 W41 W40 These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1 Bit 1 Bit 0 W41 W40 Description 0 0 Program wait not inserted when external space area 4 is accessed 1 1 program w...

Page 166: ...essed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed Initial value Bits 5 and 4 Area 2 Wait Control 1 and 0 W21 W20 These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1 Bit 5 Bit 4 W21 W20 Description 0 0 Program wait no...

Page 167: ...ea 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed Initial value Bits 1 and 0 Area 0 Wait Control 1 and 0 W01 W00 These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1 Bit 1 Bit 0 W01 W00 Description 0 0 Program wait not inserted when external space area 0 is accessed 1 1 program w...

Page 168: ...formed in different areas Bit 7 ICIS1 Description 0 Idle cycle not inserted in case of successive external read cycles in different areas 1 Idle cycle inserted in case of successive external read cycles in different areas Initial value Bit 6 Idle Cycle Insert 0 ICIS0 Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cy...

Page 169: ...S0 In advanced mode these bits select the memory interface for areas 2 to 5 When DRAM space is selected the appropriate area becomes the DRAM interface Bit 2 Bit 1 Bit 0 Description RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 0 0 Normal space 1 Normal space DRAM space 1 0 Normal space DRAM space 1 DRAM space 1 1 1 Contiguous DRAM space Note When all areas selected in DRAM are 8 bit space the P...

Page 170: ...s release is disabled BREQ BACK and BREQO can be used as I O ports Initial value 1 External bus release is enabled Bit 6 BREQO Pin Enable BREQOE Outputs a signal that requests the external bus master to drop the bus request signal BREQ in the external bus release state when an internal bus master performs an external space access or when a refresh request is generated Bit 6 BREQOE Description 0 BR...

Page 171: ...S Selects the CAS signal output timing Bit 2 RCTS Description 0 CAS signal output timing is same when reading and writing Initial value 1 When reading CAS signal is asserted half cycle earlier than when writing Bit 1 Write Data Buffer Enable WDBE This bit selects whether or not to use the write buffer function in the external write cycle or the DMAC single address cycle Bit 1 WDBE Description 0 Wr...

Page 172: ... 0D H 00 by a power on reset and in hardware standby mode It retains its previous state by a manual reset or in software standby mode Bit 7 CS0 CS7 Select CSS07 This bit selects the contents of CS output via the PG4 pin In modes 4 5 and 6 setting the corresponding DDR to 1 outputs the selected CS Bit 7 CSS07 Description 0 Selects CS0 Initial value 1 Selects CS7 Bit 6 CS3 CS6 Select CSS36 This bit ...

Page 173: ... Bit 4 LCAS Output Pin Select Bit LCASS Selects output pin for LCAS signal Bit 4 LCASS Description 0 Outputs LCAS signal from PF2 Initial value 1 Outputs LCAS signal from PF6 Bits 3 to 0 Address Output Enable 3 to 0 AE3 AE0 These bits select enabling or disabling of address outputs A8 to A23 in ROMless expanded mode and modes with ROM When a pin is enabled for address output the address is output ...

Page 174: ...ut disabled 1 0 0 0 A8 A15 address output enabled A16 A23 address output disabled 1 A8 A16 address output enabled A17 A23 address output disabled 1 0 A8 A17 address output enabled A18 A23 address output disabled 1 A8 A18 address output enabled A19 A23 address output disabled 1 0 0 A8 A19 address output enabled A20 A23 address output disabled 1 A8 A20 address output enabled A21 A23 address output d...

Page 175: ...ther the precharge cycle TP is 1 state or 2 states Bit 7 TPC Description 0 Insert 1 precharge cycle Initial value 1 Insert 2 precharge cycles Bit 6 Burst Access Enable BE This bit enables disables burst access of areas 2 to 5 allocated as DRAM space DRAM space burst access is in high speed page mode When using EDO type in this case either select OE output or RAS up mode Bit 6 BE Description 0 Burs...

Page 176: ... 8 bit access space target row addresses for comparison are A23 to A9 2 16 bit access space target row addresses for comparison are A23 to A10 1 0 10 bit shift 1 8 bit access space target row addresses for comparison are A23 to A10 2 16 bit access space target row addresses for comparison are A23 to A11 1 Bits 1 and 0 Refresh Cycle Wait Control 1 and 0 RLW1 and RLW0 These bits select the number of...

Page 177: ...ing refresh control the refresh timer can be used as an interval timer Bit 7 RFSHE Description 0 Do not perform refresh control Initial value 1 Perform refresh control Bit 6 CBR Refresh Mode CBRM This bit selects whether CBR refresh is performed in parallel with other external access or only CBR refresh is performed Bit 6 CBRM Description 0 Enables external access during CAS before RAS refresh Ini...

Page 178: ... CMF flag is set to 1 CMIE is always 0 when performing a self refresh Bit 3 CMIE Description 0 Disables CMF flag interrupt requests CMI Initial value 1 Enables CMF flag interrupt requests CMI Bits 2 to 0 Refresh Counter Clock Select CKS2 to CKS0 These bits select from the seven internal clocks derived by dividing the system clock ø to be input to RTCNT The RTCNT count up starts when CKS2 to CKS0 a...

Page 179: ...atch interrupt CMI is also generated RTCNT is initialized to H 00 at a power on reset and in hardware standby mode It is not initialized at a manual reset or in software standby mode 7 2 10 Refresh Time Constant Register RTCOR 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Bit Initial value R W RTCOR is an 8 bit read write register that sets theRTCNT compare match cycle The values...

Page 180: ...kbyte address space comprising part of area 0 Figure 7 2 shows an outline of the memory map Note Not available in the H8S 2633 Series Area 0 2Mbytes H 000000 H FFFFFF 1 2 H 0000 H 1FFFFF H 200000 Area 1 2Mbytes H 3FFFFF H 400000 Area 2 2Mbytes H 5FFFFF H 600000 Area 3 2Mbytes H 7FFFFF H 800000 Area 4 2Mbytes H 9FFFFF H A00000 Area 5 2Mbytes H BFFFFF H C00000 Area 6 2Mbytes H DFFFFF H E00000 Area 7...

Page 181: ... access 16 bit bus mode is set When the burst ROM interface is designated 16 bit bus mode is always set 2 Number of Access States Two or three access states can be selected with ASTCR An area for which 2 state access is selected functions as a 2 state access space and an area for which 3 state access is selected functions as a 3 state access space With the DRAM interface or the burst ROM interface...

Page 182: ...eries memory interfaces comprise a basic bus interface that allows direct connection or ROM SRAM and so on DRAM interface with direct DRAM connection and a burst ROM interface that allows direct connection of burst ROM The memory interface can be selected independently for each area An area for which the basic bus interface is designated functions as normal space and areas set for DRAM interface a...

Page 183: ... space CS1 and CS6 pin signals can be output when accessing the area 1 and 6 external space Only the basic bus interface can be used for areas 1 and 6 Areas 2 to 5 In external expansion mode all of areas 2 to 5 is external space CS2 to CS5 signals can be output when accessing area 2 to 5 external space The standard bus interface or DRAM interface can be selected for areas 2 to 5 In DRAM interface ...

Page 184: ...d expanded mode the CS0 pin is set for output after a power on reset The CS1 to CS7 pins are set for input after a power on reset so the corresponding DDR must be set to 1 to allow the output of CS1 to CS7 signals In ROM disabled expanded mode all of pins CS0 to CS7 are set for input after a power on reset so the corresponding DDR must be set to 1 to allow the output of CS0 to CS7 signals See Sect...

Page 185: ...bus specifications for the area being accessed 8 bit access space or 16 bit access space and the data size 8 Bit Access Space Figure 7 4 illustrates data alignment control for the 8 bit access space With the 8 bit access space the upper data bus D15 to D8 is always used for accesses The amount of data that can be accessed at one time is one byte a word transfer instruction is performed as two byte...

Page 186: ...a longword transfer instruction is executed as two word transfer instructions In byte access whether the upper or lower data bus is used is determined by whether the address is even or odd The upper data bus is used for an even address and the lower data bus for an odd address D15 D8 D7 D0 Upper data bus Byte size Word size 1st bus cycle 2nd bus cycle Longword size Even address Byte size Odd addre...

Page 187: ...s and the LWR signal for the lower half Table 7 4 Data Buses Used and Valid Strobes Area Access Size Read Write Address Valid Strobe Upper Data Bus D15 to D8 Lower data bus D7 to D0 8 bit access Byte Read RD Valid Invalid space Write HWR Hi Z 16 bit access Byte Read Even RD Valid Invalid space Odd Invalid Valid Write Even HWR Valid Hi Z Odd LWR Hi Z Valid Word Read RD Valid Valid Write HWR LWR Val...

Page 188: ...ccess space is accessed the upper half D15 to D8 of the data bus is used The LWR pin is fixed high Wait states cannot be inserted Bus cycle T1 T2 Address bus ø AS CSn RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 High impedance Write Note n 0 to 7 High Figure 7 6 Bus Timing for 8 Bit 2 State Access Space ...

Page 189: ...e is accessed the upper half D15 to D8 of the data bus is used The LWR pin is fixed high Wait states can be inserted Bus cycle T1 T2 Address bus ø AS CSn RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 High impedance Write High Note n 0 to 7 T3 Figure 7 7 Bus Timing for 8 Bit 3 State Access Space ...

Page 190: ... to D8 of the data bus is used for the even address and the lower half D7 to D0 for the odd address Wait states cannot be inserted Bus cycle T1 T2 Address bus ø AS CSn RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 High impedance Write High Note n 0 to 7 Figure 7 8 Bus Timing for 16 Bit 2 State Access Space 1 Even Address Byte Access ...

Page 191: ... T2 Address bus ø AS CSn RD D15 to D8 Invalid D7 to D0 Valid Read HWR LWR D15 to D8 High impedance D7 to D0 Valid Write Note n 0 to 7 High Figure 7 9 Bus Timing for 16 Bit 2 State Access Space 2 Odd Address Byte Access ...

Page 192: ... Bus cycle T1 T2 Address bus ø AS CSn RD D15 to D8 Valid D7 to D0 Valid Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write Note n 0 to 7 Figure 7 10 Bus Timing for 16 Bit 2 State Access Space 3 Word Access ...

Page 193: ... to D8 of the data bus is used for the even address and the lower half D7 to D0 for the odd address Wait states can be inserted Bus cycle T1 T2 Address bus ø AS CSn RD D15 to D8 Valid D7 to D0 Invalid Read HWR LWR D15 to D8 Valid D7 to D0 High impedance Write High Note n 0 to 7 T3 Figure 7 11 Bus Timing for 16 Bit 3 State Access Space 1 Even Address Byte Access ...

Page 194: ...2 Address bus ø AS CSn RD D15 to D8 Invalid D7 to D0 Valid Read HWR LWR D15 to D8 High impedance D7 to D0 Valid Write High Note n 0 to 7 T3 Figure 7 12 Bus Timing for 16 Bit 3 State Access Space 2 Odd Address Byte Access ...

Page 195: ...Bus cycle T1 T2 Address bus ø AS CSn RD D15 to D8 Valid D7 to D0 Valid Read HWR LWR D15 to D8 Valid D7 to D0 Valid Write Note n 0 to 7 T3 Figure 7 13 Bus Timing for 16 Bit 3 State Access Space 3 Word Access ...

Page 196: ... state access space according to the settings of WCRH and WCRL Pin Wait Insertion Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin Program wait insertion is first carried out according to the settings in WCRH and WCRL Then if the WAIT pin is low at the falling edge of ø in the last T2 or Tw state a Tw state is inserted If the WAIT pin is held low Tw states are ins...

Page 197: ...te indicates the timing of WAIT pin sampling WAIT Data bus T2 Tw Tw Tw T3 By WAIT pin Figure 7 14 Example of Wait State Insertion Timing The settings after a power on reset are 3 state access 3 program wait state insertion and WAIT input disabled At a manual reset the bus control register values are retained and wait control continues as before the reset ...

Page 198: ...onship between the settings of the RMTS2 to RMTS0 bits and DRAM space You can select 1 one area area 2 2 two areas areas 2 and 3 or 3 four areas areas 2 to 5 Using 16 64M DRAMs requires a 4M word 8MB contiguous space Setting RMTS2 to RMTS0 to 1 allows areas 2 to 5 to be configured as one contiguous DRAM space The RAS signal can be output from the CS2 pin and CS3 to CS5 can be used as input ports I...

Page 199: ...23 to A13 A12 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 1 0 10 bits A23 to A13 A12 A11 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 1 Do not set Column address A23 to A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 7 5 4 Data Bus Setting the ABWCR bit of an area set as DRAM space to 1 sets the corresponding area as 8 bit DRAM space Clearing the ABWCR bit to 0 sets the area as 16 bit DRAM 16 bit ...

Page 200: ...ddress strobe Output Upper column address strobe when accessing DRAM space WAIT WAIT Wait Input Wait request signal A12 to A0 A12 to A0 Address pin Output Multiplexed output of row address and column address D15 to D0 D15 to D0 Data pin Input output Data input output pin OE OE Output enable pin Output Output enable signal when accessing DRAM space in read mode Note Valid when OES bit set to 1 7 5 ...

Page 201: ...iffers when reading and writing being asserted Ω cycle earlier when reading Tp ø CSn RAS Read Write CAS LCAS CAS LCAS HWR WE RD AS RD D15 toD0 HWR WE D15 to D0 A23 to A0 Tr Tc1 Tc2 row column Note n 2 to 5 RCTS 1 RCTS 0 Figure 7 15 Basic Access Timing ...

Page 202: ...om 1 state to 2 states Set the appropriate number of TP cycles according to the type of DRAM connected and the operation frequency of the LSI Figure 7 16 shows the timing when TP is set for 2 states Setting the TPC bit to 1 also sets the refresh cycle TP to 2 states Tp1 ø Read Write D15 to D0 D15 to D0 A23 to A0 Tp2 Tr Tc1 row column Tc2 Note n 2 to 5 CSn RAS CAS LCAS CAS LCAS HWR WE HWR WE RCTS 0...

Page 203: ... between the Tc1 state and Tc2 state When a program wait is inserted the write wait function is activated and only the CAS signal is output only during the Tc2 state when writing Figure 7 17 shows example timing for the insertion of program waits Program waits Tp Address bus ø CSn RAS CAS LCAS Data bus Read data Read CAS LCAS HWR WE RD AS Write data Write Note shows timing for WAIT pin sampling Da...

Page 204: ... kept Low Tw is inserted until the level of the WAIT pin changes to High When wait states are inserted via the WAIT pin the CAS when writing is output after the Tw state Figure 7 18 shows example timing for the insertion of wait states via the WAIT pin WAIT pin wait states Program waits Tp Address bus ø CSn RAS CAS LCAS Data bus Read data Read CAS LCAS HWR WE RD AS Write data Write Note shows timi...

Page 205: ...page mode When all areas selected as DRAM space are set as 8 bit space the LCAS pin functions as an I O port Tp ø CSn RAS Byte control A23 to A0 Tr Tc1 Tc2 row CAS LCAS HWR WE column Note n 2 to 5 Figure 7 19 2 CAS Method Control Timing For High Byte Write Access When using DRAM EDO page mode either use OE to control the read data or as shown in Figure 7 20 select RAS up mode Figure 7 21 is an exa...

Page 206: ...t DRAM 256KB 16 bit configuration 9 bit column address OE RAS CAS UCAS LCAS LCAS HWR WE WE A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 D15 to D0 Row address input A8 to A0 Column address input A8 to A0 Figure 7 20 High speed Page Mode DRAM ...

Page 207: ... A0 Figure 7 21 Example Connection of EDO Page Mode DRAM OES 1 7 5 10 Burst Operation In addition to full DRAM access normal DRAM access in which the row address is output each time the data in DRAM is accessed there is also a high speed page mode that allows high speed access burst access In this method if the same row address is accessed successively the row address is output once and then only ...

Page 208: ...es The MXC1 and MXC0 bits of the MCR specify which row address is compared Tp ø CSn RAS Read Write CAS LCAS CAS LCAS AS OE OE HWR WE D15 to D0 HWR WE D15 to D0 A23 to A0 Tr Tc1 Tc2 row column1 column2 Tc1 Tc2 Note n 2 to 5 OE is enabled when OES 1 RCTS 1 RCTS 0 Figure 7 22 Operating Timing in High Speed Page Mode The bus cycle can also be extended in burst access by inserting wait states The metho...

Page 209: ... 1 When DRAM access is interrupted and another area accessed the RAS signal level is kept Low and if the row address is the same as previously when the DRAM space is again accessed burst access is continued Figure 7 23 shows example RAS down mode timing Note that if the refresh operation occurs when RAS is down the RAS signal level changes to High External space read access Tp A23 to A0 ø CSn RAS ...

Page 210: ... only possible when the DRAM space is contiguous Figure 7 24 shows example timing in RAS up mode Note that the RAS signal level does not return to High in burst ROM space access External space write access Tp A23 to A0 ø Tr Tc1 Tc2 Tc1 Tc2 DRAM read access DRAM write access T1 T2 D15 to D0 Note n 2 to 5 CSn RAS CAS LCAS RD HWR WE Figure 7 24 Example Operation Timing in RAS Up Mode ...

Page 211: ...r the DRAM being used The RTCNT count up starts when the CKS2 to CKS0 bits are set The RTCNT and RTCOR values should therefore be set before setting CKS2 to CKS0 When a value is set in RTCOR RTCNT is cleared When RTCNT is set at the same time that it is reset by a compare match the value written to RTCNT takes precedence When performing refresh control RFSHE 1 do not clear the CMF flag Figure 7 25...

Page 212: ...resh request signal and CMF bit setting signal Figure 7 26 Compare Match Timing A23 to A0 ø Read access of normal space RAS CAS HWR WE CS AS RD Write access of normal space Refresh cycle Figure 7 27 Example CBR Refresh Timing CBRM 0 ...

Page 213: ...187 A23 to A0 ø Normal space access request RAS CAS HWR WE CS AS RD Refresh cycle Figure 7 28 Example CBR Refresh Timing CBRM 1 ...

Page 214: ...s are output and the DRAM enters self refresh mode When you exit software standby mode the RMODE bit is cleared to 0 and self refresh mode is exited When making a transition to software standby mode self refresh mode starts after a CBR refresh providing there is a CBR refresh request CBR refresh requests occurring immediately before entering software standby mode are cleared on completion of the s...

Page 215: ...Burst access is performed on the basis of the address only regardless of the bus master The DACK output level changes to Low afer the Tc1 state in the case of the DRAM interface Figure 7 30 shows the DACK output timing for the DRAM interface when DDS 1 Tp ø Read Write D15 to D0 D15 to D0 A23 to A0 Tr Tc1 Tc2 row column CSn RAS CAS UCAS LCAS LCAS CAS UCAS LCAS LCAS DACK HWR WE HWR WE RCTS 1 RCTS 0 ...

Page 216: ...ce In other than DMAC signle address mode burst access is possible when the DRAM space is accessed Figure 7 31 shows the DACK output timing for the DRAM interface when DDS 0 Tp ø Read Write Note n 2 to 5 D15 to D0 D15 to D0 A23 to A0 Tr Tc1 Tc2 row column CSn RAS CAS UCAS LCAS LCAS CAS UCAS LCAS LCAS DACK HWR WE HWR WE RCTS 1 RCTS 0 Figure 7 31 DACK Output Timing when DDS 0 Example Showing DRAM Ac...

Page 217: ...f access states in the initial cycle full access of the burst ROM interface Wait states can be inserted when the AST0 bit is set to 1 The burst cycle can be set for 1 state or 2 sttes by setting the BRSTS1 bit of BCRH Wait states cannot be inserted When area 0 is set as burst ROM space area 0 is a 16 bit access space regardless of the ABW0 bit of ABWCR When the BRSTS0 bit of BCRH is cleared to 0 4...

Page 218: ...192 T1 Address bus ø CS0 AS Data bus T2 T3 T1 T2 T1 Full access T2 RD Burst access Low address only changes Read data Read data Read data Figure 7 32 a Example Burst ROM Access Timing AST0 BRSTS1 1 ...

Page 219: ...gure 7 32 b Example Burst ROM Access Timing AST0 BRSTS1 0 7 7 3 Wait Control As with the basic bus interface either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle full access of the burst ROM interface See Section 7 4 5 Wait Control Wait states cannot be inserted in the burst cycle ...

Page 220: ...dle cycle is inserted at the start of the second read cycle Figure 7 33 shows an example of the operation in this case In this example bus cycle A is a read cycle from ROM with a long output floating time and bus cycle B is a read cycle from SRAM each being located in a different area In a an idle cycle is not inserted and a collision occurs in cycle B between the read data from ROM and that from ...

Page 221: ...is a CPU write cycle In a an idle cycle is not inserted and a collision occurs in cycle B between the read data from ROM and the CPU write data In b an idle cycle is inserted and a data collision is prevented T1 Address bus ø RD Bus cycle A T2 T3 T1 T2 Bus cycle B Possibility of overlap between CS area B and RD T1 Address bus ø Bus cycle A T2 T3 TI T1 Bus cycle B T2 CS area A CS area B RD CS area ...

Page 222: ... signal Setting idle cycle insertion as in b however will prevent any overlap between the RD and CS signals In the initial state after reset release idle cycle insertion b is set T1 Address bus ø RD Bus cycle A Data bus T2 T3 T1 T2 Bus cycle B Long output floating time Data collision T1 Address bus ø RD Bus cycle A Data bus T2 T3 TI T1 Bus cycle B T2 HWR HWR CS area A CS area B CS area A CS area B...

Page 223: ...CIS0 and ICIS1 settings are valid in burst access in RAS down mode and an idle cycle is inserted Figure 7 37 a and b shows the timing T1 Address bus ø RD External read Data bus T2 T3 Tp Tr DRAM space read Tc1 Tc2 Figure 7 36 Example of DRAM Access after External Read EXTAL Address RD RAS CAS LCAS Data bus DRAM space read Tp Tr Tc1 Tc2 T1 T1 T2 T3 Tc1 Tc1 Tc2 External read DRAM space read Idle cycl...

Page 224: ...le Idle Cycle Operation in RAS Down Mode ICIS0 1 7 8 2 Pin States in Idle Cycle Table 7 8 shows pin states in an idle cycle Table 7 8 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of next bus cycle D15 to D0 High impedance CSn High CAS High AS High RD High HWR High LWR High DACKn High Note Remains low in DRAM space RAS down mode or a refresh cycle ...

Page 225: ...external write and DMA single address mode transmission continues for 2 states or longer and there is an internal access next only an external write is executed in the first state but from the next state onward an internal access on chip memory or internal I O register read write is executed in parallel with the external write rather than waiting until it ends T1 Internal address bus A23 to A0 Ext...

Page 226: ... master wants to make an external access it temporarily defers activation of the bus cycle and waits for the bus request from the external bus master to be dropped Also when a refresh request occurs in the external bus released state refresh control is deferred until the external bus master drops the bus request If the BREQOE bit in BCRL is set to 1 when an internal bus master wants to make an ext...

Page 227: ... states in the external bus released state Table 7 9 Pin States in Bus Released State Pins Pin State A23 to A0 High impedance D15 to D0 High impedance CSn High impedance CAS High impedance AS High impedance RD High impedance HWR High impedance LWR High impedance DACKn High ...

Page 228: ...o 1 Low level of BREQ pin is sampled at rise of T2 state BACK pin is driven low at end of CPU read cycle releasing bus to external bus master BREQ pin state is still sampled in external bus released state High level of BREQ pin is sampled BACK pin is driven high ending bus release cycle BREQO signal goes high 1 5 clocks after BACK signal goes high High impedance High impedance High impedance High ...

Page 229: ...n is deactivated when MSTPCR is set to H FFFFFF or H EFFFFF and a transition is made to sleep mode To use the external bus release function in sleep mode do not set MSTPCR to H FFFFFF and H EFFFFF When the CBRM bit is set to 1 to use the CBR refresh function set the BREQ 1 width greater than the number of the slowest external access states Otherwise CBR refresh requests from the refresh timer may ...

Page 230: ...al to the bus master making the request If there are bus requests from more than one bus master the bus request acknowledge signal is sent to the one with the highest priority When a bus master receives the bus request acknowledge signal it takes possession of the bus until that signal is canceled The order of priority of the bus masters is as follows High DMAC DTC CPU Low An internal bus access b...

Page 231: ...t is generated The DTC can release the bus after a vector read a register information read 3 states a single data transfer or a register information write 3 states It does not release the bus during a register information read 3 states a single data transfer or a register information write 3 states DMAC When a start request occurs the DMAC requests the bus arbiter for bus privileges The DMAC relea...

Page 232: ...pecified as 24 bits In single address mode transfer can be performed in one bus cycle Choice of sequential mode idle mode or repeat mode for dual address mode and single address mode Full address mode Maximum of 2 channels can be used Transfer source and transfer destination address specified as 24 bits Choice of normal mode or block transfer mode 16 Mbyte address space can be specified directly B...

Page 233: ...CK1 Interrupt signals DEND0A DEND0B DEND1A DEND1B Control logic DMAWER DMACR1B DMACR1A DMACR0B DMACR0A DMATCR DMABCR Data buffer Internal data bus MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B Legend DMA write enable register DMA terminal control register DMA band control register for all channels DMA control register Memory address register I O address register E...

Page 234: ...request Memory address fixed 1 to 65536 transfers Repeat mode 1 byte or 1 word transfer executed for one transfer request Memory address incremented decremented by 1 or 2 After specified number of transfers 1 to 256 initial state is restored and operation continues TPU channel 0 to 5 compare match input capture A interrupt SCI transmit data empty interrupt SCI reception complete interrupt A D conv...

Page 235: ...request 24 24 External request 1 byte or 1 word transfer executed for one transfer request 1 to 65536 transfers External request Block transfer mode Specified block size transfer executed for one transfer request 1 to 65536 transfers Either source or destination specifiable as block area Block size 1 to 256 bytes or words TPU channel 0 to 5 compare match input capture A interrupt SCI transmit data...

Page 236: ...nding port to output functioning as a DACK pin With regard to the TEND pins whether or not the corresponding port is used as a TEND pin can be specified by means of a register setting Table 8 2 DMAC Pins Channel Pin Name Symbol I O Function 0 DMA request 0 DREQ0 Input DMAC channel 0 external request DMA transfer acknowledge 0 DACK0 Output DMAC channel 0 single address transfer acknowledge DMA tran...

Page 237: ...address register 1A IOAR1A R W Undefined H FEF4 16 bits Transfer count register 1A ETCR1A R W Undefined H FEF6 16 bits Memory address register 1B MAR1B R W Undefined H FEF8 16 bits I O address register 1B IOAR1B R W Undefined H FEFC 16 bits Transfer count register 1B ETCR1B R W Undefined H FEFE 16 bits 0 1 DMA write enable register DMAWER R W H 00 H FF60 8 bits DMA terminal control register DMATCR...

Page 238: ... transfer destination address Specifies transfer destination transfer source address Specifies number of transfers Specifies transfer size mode activation source etc Specifies transfer source transfer destination address Specifies transfer destination transfer source address Specifies number of transfers Specifies transfer size mode activation source etc IOAR0A ETCR0A DMACR0A Channel 0B MAR0B IOAR...

Page 239: ...that specifies the transfer source address or destination address The upper 8 bits of MAR are reserved they are always read as 0 and cannot be modified Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR MAR is incremented or decremented each time a byte or word transfer is executed so that the address speci...

Page 240: ...ransfer is executed so that the address specified by IOAR is fixed IOAR is not initialized by a reset or in standby mode 8 2 3 Execute Transfer Count Register ETCR ETCR is a 16 bit readable writable register that specifies the number of transfers The setting of this register is different for sequential mode and idle mode on the one hand and for repeat mode on the other 1 Sequential Mode and Idle M...

Page 241: ...eaches H 00 ETCRL is loaded with the value in ETCRH At this point MAR is automatically restored to the value it had when the count was started The DTE bit in DMABCR is not cleared and so transfers can be performed repeatedly until the DTE bit is cleared by the user ETCR is not initialized by a reset or in standby mode 8 2 4 DMA Control Register DMACR Bit 7 6 5 4 3 2 1 0 DMACR DTSZ DTID RPE DTDIR D...

Page 242: ...DTSZ 1 MAR is decremented by 2 after a transfer Bit 5 Repeat Enable RPE Used in combination with the DTIE bit in DMABCR to select the mode sequential idle or repeat in which transfer is to be performed Bit 5 DMABCR RPE DTIE Description 0 0 Transfer in sequential mode no transfer end interrupt Initial value 1 Transfer in sequential mode with transfer end interrupt 1 0 Transfer in repeat mode no tra...

Page 243: ...1 DTF0 Description 0 0 0 0 Initial value 1 Activated by A D converter conversion end interrupt 1 0 1 1 0 0 Activated by SCI channel 0 transmit data empty interrupt 1 Activated by SCI channel 0 reception complete interrupt 1 0 Activated by SCI channel 1 transmit data empty interrupt 1 Activated by SCI channel 1 reception complete interrupt 1 0 0 0 Activated by TPU channel 0 compare match input capt...

Page 244: ... match input capture A interrupt 1 Activated by TPU channel 1 compare match input capture A interrupt 1 0 Activated by TPU channel 2 compare match input capture A interrupt 1 Activated by TPU channel 3 compare match input capture A interrupt 1 0 0 Activated by TPU channel 4 compare match input capture A interrupt 1 Activated by TPU channel 5 compare match input capture A interrupt 1 0 1 Note Detec...

Page 245: ...MAC channel DMABCR is initialized to H 0000 by a reset and in standby mode Bit 15 Full Address Enable 1 FAE1 Specifies whether channel 1 is to be used in short address mode or full address mode In short address mode channels 1A and 1B are used as independent channels Bit 15 FAE1 Description 0 Short address mode Initial value 1 Full address mode Bit 14 Full Address Enable 0 FAE0 Specifies whether c...

Page 246: ...factor setting When DTE 1 and DTA 1 the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer When DTE 1 and DTA 1 the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC When DTE 1 and DTA 0 the internal interrupt source selected by the data transfer factor setting is...

Page 247: ...e selected by the channel 0B data transfer factor setting Bit 9 DTA0B Description 0 Clearing of selected internal interrupt source at time of DMA transfer is disabled Initial value 1 Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 8 Data Transfer Acknowledge 0A DTA0A Enables or disables clearing when DMA transfer is performed of the internal interrupt source s...

Page 248: ...s issued by the activation source DMA transfer is executed The condition for the DTE bit being set to 1 is as follows When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 7 Data Transfer Enable 1B DTE1B Enables or disables data transfer on channel 1B Bit 7 DTE1B Description 0 Data transfer disabled Initial value 1 Data transfer enabled Bit 6 Data Transfer Enable 1A DTE1A Enables or ...

Page 249: ...r again and then setting the DTE bit to 1 Bit 3 Data Transfer End Interrupt Enable 1B DTIE1B Enables or disables the channel 1B transfer end interrupt Bit 3 DTIE1B Description 0 Transfer end interrupt disabled Initial value 1 Transfer end interrupt enabled Bit 2 Data Transfer End Interrupt Enable 1A DTIE1A Enables or disables the channel 1A transfer end interrupt Bit 2 DTIE1A Description 0 Transfe...

Page 250: ...W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Undefined MAR is a 32 bit readable writable register MARA functions as the transfer source address register and MARB as the destination address register MAR is composed of two 16 bit registers MARH and MARL The upper 8 bits of MARH are reserved they are always read as 0 and cannot be modified MAR is incremented or decremented each t...

Page 251: ...ial value R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Undefined In normal mode ETCRA functions as a 16 bit transfer counter ETCRA is decremented by 1 each time a transfer is performed and transfer ends when the count reaches H 0000 ETCRB is not used at this time ETCRB ETCRB is not used in normal mode 2 Block Transfer Mode ETCRA Holds block size Bit 15 14 13 12 11 10 9 8 ETC...

Page 252: ...sired number of bytes or words ETCRB functions in block transfer mode as a 16 bit block transfer counter ETCRB is decremented by 1 each time a block is transferred and transfer ends when the count reaches H 0000 8 3 4 DMA Control Register DMACR DMACR is a 16 bit readable writable register that controls the operation of each DMAC channel In full address mode DMACRA and DMACRB have different functio...

Page 253: ...1 MARA is incremented by 2 after a transfer 1 0 MARA is fixed 1 MARA is decremented after a data transfer When DTSZ 0 MARA is decremented by 1 after a transfer When DTSZ 1 MARA is decremented by 2 after a transfer Bit 12 Block Direction BLKDIR Bit 11 Block Enable BLKE These bits specify whether normal mode or block transfer mode is to be used If block transfer mode is specified the BLKDIR bit spec...

Page 254: ...RB is incremented by 2 after a transfer 1 0 MARB is fixed 1 MARB is decremented after a data transfer When DTSZ 0 MARB is decremented by 1 after a transfer When DTSZ 1 MARB is decremented by 2 after a transfer Bit 4 Reserved Can be read or written to Bits 3 to 0 Data Transfer Factor DTF3 to DTF0 These bits select the data transfer factor activation source The factors that can be specified differ b...

Page 255: ...mpare match input capture A interrupt 1 Activated by TPU channel 1 compare match input capture A interrupt 1 0 Activated by TPU channel 2 compare match input capture A interrupt 1 Activated by TPU channel 3 compare match input capture A interrupt 1 0 0 Activated by TPU channel 4 compare match input capture A interrupt 1 Activated by TPU channel 5 compare match input capture A interrupt 1 0 1 Note ...

Page 256: ...R is initialized to H 0000 by a reset and in standby mode Bit 15 Full Address Enable 1 FAE1 Specifies whether channel 1 is to be used in short address mode or full address mode In full address mode channels 1A and 1B are used together as a single channel Bit 15 FAE1 Description 0 Short address mode Initial value 1 Full address mode Bit 14 Full Address Enable 0 FAE0 Specifies whether channel 0 is t...

Page 257: ...er When the DTE 0 the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting The state of the DTME bit does not affect the above operations Bit 11 Data Transfer Acknowledge 1 DTA1 Enables or disables clearing when DMA transfer is performed of the internal interrupt source selected by the channel 1 data ...

Page 258: ...ever the DTME bit is not cleared by an NMI interrupt and transfer is not interrupted The conditions for the DTME bit being cleared to 0 are as follows When initialization is performed When NMI is input in burst mode When 0 is written to the DTME bit The condition for DTME being set to 1 is as follows When 1 is written to DTME after DTME is read as 0 Bit 7 Data Transfer Master Enable 1 DTME1 Enable...

Page 259: ...est is issued by the activation source DMA transfer is executed The condition for the DTE bit being set to 1 is as follows When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 6 Data Transfer Enable 1 DTE1 Enables or disables data transfer on channel 1 Bit 6 DTE1 Description 0 Data transfer disabled Initial value 1 Data transfer enabled Bit 4 Data Transfer Enable 0 DTE0 Enables or d...

Page 260: ... 0 the DMAC regards this as indicating the end of a transfer and issues a transfer end interrupt request to the CPU or DTC A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt handling routine or by performing processing to continue transfer by setting the transfer counter and address register again and then setting the DTE bit to 1 Bit 2 Data Transfer En...

Page 261: ...or the DTC Figure 8 2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt and reactivating channel 0A The address register and count register area is re set by the first DTC transfer then the control register area is re set by the second DTC chain transfer When re setting the control register area perform masking by setting bits in DMAWER to prevent modificatio...

Page 262: ...ABCR and bit 5 in DMATCR are disabled Initial value 1 Writes to all bits in DMACR1B bits 11 7 and 3 in DMABCR and bit 5 in DMATCR are enabled Bit 2 Write Enable 1A WE1A Enables or disables writes to all bits in DMACR1A and bits 10 6 and 2 in DMABCR by the DTC Bit 2 WE1A Description 0 Writes to all bits in DMACR1A and bits 10 6 and 2 in DMABCR are disabled Initial value 1 Writes to all bits in DMAC...

Page 263: ...annel to be reactivated MAR IOAR and ETCR are always write enabled regardless of the DMAWER settings When modifying these registers the channel for which the modification is to be made should be halted 8 4 2 DMA Terminal Control Register DMATCR Bit 7 6 5 4 3 2 1 0 DMATCR TEE1 TEE0 Initial value 0 0 0 0 0 0 0 0 R W R W R W DMATCR is an 8 bit readable writable register that controls enabling or disa...

Page 264: ...nnot be modified 8 4 3 Module Stop Control Register MSTPCR Bit 7 6 5 4 3 2 1 0 MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value 0 0 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W MSTPCRA is a 8 bit readable writable register that performs module stop mode control When the MSTPA7 bit in MSTPCR is set to 1 the DMAC operation stops at the end of the bus cycle and a transition is...

Page 265: ...o 4 channels can operate independently External request applies to channel B only Single address mode applies to channel B only Modes 1 2 and 3 can also be specified for single address mode 4 Single address mode Full address mode 5 Normal mode External request Auto request Max 2 channel operation combining channels A and B 6 Block transfer mode TPU channel 0 to 5 compare match input capture A inte...

Page 266: ...r original settings and operation is continued No interrupt request is sent to the CPU or DTC One address is specified as 24 bits and the other as 16 bits The transfer direction is programmable 4 Single address mode In response to a single transfer request the specified number of transfers are carried out between external memory and an external device one byte or one word at a time Unlike dual add...

Page 267: ...ring the RPE bit in DMACR to 0 In sequential mode MAR is updated after each byte or word transfer in response to a single transfer request and this is executed the number of times specified in ETCR One address is specified by MAR and the other by IOAR The transfer direction can be specified by the DTDIR bit in DMACR Table 8 6 summarizes register functions in sequential mode Table 8 6 Register Func...

Page 268: ...er IOAR 1 byte or word transfer performed in response to 1 transfer request Legend Address T L Address B L 1 DTID 2DTSZ N 1 Where L Value set in MAR N Value set in ETCR Figure 8 3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR ETCR is decremented by 1 each time a transfer is executed and when its value reaches H 0000 the DTE bit is cleared and transfer ends If...

Page 269: ...e FAE bit to 0 to select short address mode Specify enabling or disabling of internal interrupt clearing with the DTA bit 2 Set the transfer source address and transfer destination address in MAR and IOAR 3 Set the number of transfers in ETCR 4 Set each bit in DMACR Set the transfer data size with the DTSZ bit Specify whether MAR is to be incremented or decremented with the DTID bit Clear the RPE ...

Page 270: ...register Destination address register Start address of transfer destination or transfer source Fixed 23 0 IOAR 15 H FF Destination address register Source address register Start address of transfer source or transfer destination Fixed 0 15 ETCR Transfer counter Number of transfers Decremented every transfer transfer ends when count reaches H 0000 Legend MAR Memory address register IOAR I O address...

Page 271: ...s cleared and transfer ends If the DTIE bit is set to 1 at this time an interrupt request is sent to the CPU or DTC The maximum number of transfers when H 0000 is set in ETCR is 65 536 Transfer requests activation sources consist of A D converter conversion end interrupts external requests SCI transmission complete and reception complete interrupts and TPU channel 0 to 5 compare match input captur...

Page 272: ... with the DTA bit 2 Set the transfer source address and transfer destination address in MAR and IOAR 3 Set the number of transfers in ETCR 4 Set each bit in DMACR Set the transfer data size with the DTSZ bit Specify whether MAR is to be incremented or decremented with the DTID bit Set the RPE bit to 1 Specify the transfer direction with the DTDIR bit Select the activation source with bits DTF3 to ...

Page 273: ...ctions in repeat mode Table 8 8 Register Functions in Repeat Mode Function Register DTDIR 0 DTDIR 1 Initial Setting Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source Incremented decremented every transfer Initial setting is restored when value reaches H 0000 23 0 IOAR 15 H FF Destination address register Source address ...

Page 274: ... ETCRL is decremented by 1 each time a transfer is executed and when its value reaches H 00 it is loaded with the value in ETCRH At the same time the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR The MAR restoration operation is as shown below MAR MAR 1 DTID 2DTSZ ETCRH The same value should be set in ETCRH and ETCRL In repeat mode operation continue...

Page 275: ...s B L 1 DTID 2DTSZ N 1 Where L Value set in MAR N Value set in ETCR Figure 8 7 Operation in Repeat mode Transfer requests activation sources consist of A D converter conversion end interrupts external requests SCI transmission complete and reception complete interrupts and TPU channel 0 to 5 compare match input capture A interrupts External requests can be set for channel B only ...

Page 276: ...he DTA bit 2 Set the transfer source address and transfer destination address in MAR and IOAR 3 Set the number of transfers in both ETCRH and ETCRL 4 Set each bit in DMACR Set the transfer data size with the DTSZ bit Specify whether MAR is to be incremented or decremented with the DTID bit Set the RPE bit to 1 Specify the transfer direction with the DTDIR bit Select the activation source with bits...

Page 277: ...Operation 23 0 MAR Source address register Destination address register Start address of transfer destination or transfer source DACK pin Write strobe Read strobe Set automatically by SAE bit IOAR is invalid Strobe for external device 0 15 ETCR Transfer counter Number of transfers Legend MAR Memory address register IOAR I O address register ETCR Transfer count register DTDIR Data transfer directio...

Page 278: ...s specified Address T Address B Transfer DACK 1 byte or word transfer performed in response to 1 transfer request Legend Address T L Address B L 1 DTID 2DTSZ N 1 Where L Value set in MAR N Value set in ETCR Figure 8 9 Operation in Single Address Mode When Sequential Mode is Specified ...

Page 279: ...g with the DTA bit 2 Set the transfer source address transfer destination address in MAR 3 Set the number of transfers in ETCR 4 Set each bit in DMACR Set the transfer data size with the DTSZ bit Specify whether MAR is to be incremented or decremented with the DTID bit Clear the RPE bit to 0 to select sequential mode Specify the transfer direction with the DTDIR bit Select the activation source wi...

Page 280: ...art address of transfer destination Incremented decremented every transfer or fixed 0 15 ETCRA Transfer counter Number of transfers Decremented every transfer transfer ends when count reaches H 0000 Legend MARA Memory address register A MARB Memory address register B ETCRA Transfer count register A MARA and MARB specify the start addresses of the transfer source and transfer destination respective...

Page 281: ... LA LB N Figure 8 11 Operation in Normal Mode Transfer requests activation sources are external requests and auto requests With auto request the DMAC is only activated by register setting and the specified number of transfers are performed automatically With auto request cycle steal mode or burst mode can be selected In cycle steal mode the bus is released to another bus master each time a transfe...

Page 282: ... MARA and the transfer destination address in MARB 3 Set the number of transfers in ETCRA 4 Set each bit in DMACRA and DMACRB Set the transfer data size with the DTSZ bit Specify whether MARA is to be incremented decremented or fixed with the SAID and SAIDE bits Clear the BLKE bit to 0 to select normal mode Specify whether MARB is to be incremented decremented or fixed with the DAID and DAIDE bits...

Page 283: ... MARA Source address register Start address of transfer source Incremented decremented every transfer or fixed 23 0 MARB Destination address register Start address of transfer destination Incremented decremented every transfer or fixed 0 ETCRAH 7 0 ETCRAL 7 Holds block size Block size counter Block size Block size Fixed Decremented every transfer ETCRH value copied when count reaches H 00 15 0 ETC...

Page 284: ... operation in block transfer mode when MARB is designated as a block area Address TA Address BA Transfer Address TB Address BB 1st block 2nd block Nth block Block area Consecutive transfer of M bytes or words is performed in response to one request Legend Address Address Address Address Where LA LB LA SAIDE 1 SAID 2DTSZ M N 1 LB DAIDE 1 DAID 2DTSZ N 1 Value set in MARA Value set in MARB Value set ...

Page 285: ...ock Nth block Block area Consecutive transfer of M bytes or words is performed in response to one request Legend Address Address Address Address Where LA LB LA SAIDE 1 SAID 2DTSZ N 1 LB DAIDE 1 DAID 2DTSZ M N 1 Value set in MARA Value set in MARB Value set in ETCRB Value set in ETCRAH and ETCRAL TA TB BA BB LA LB N M Figure 8 14 Operation in Block Transfer Mode BLKDIR 1 ...

Page 286: ... value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ SAID DAID and SAIDE DAIDE bits in DMACR ETCRB is decremented by 1 every block transfer and when the count reaches H 0000 the DTE bit is cleared and transfer ends If the DTIE bit is set to 1 at this point an interrupt request is sent to the CPU or DTC Figure 8 ...

Page 287: ...B MARB DAIDE 1 DAID 2DTSZ MARB MARB DAIDE 1 DAID 2DTSZ ETCRAH MARA MARA SAIDE 1 SAID 2DTSZ ETCRAH No Yes No Yes No Yes No Yes Clear DTE bit to 0 to end transfer Figure 8 15 Operation Flow in Block Transfer Mode Transfer requests activation sources consist of A D converter conversion end interrupts external requests SCI transmission complete and reception complete interrupts and TPU channel 0 to 5 ...

Page 288: ... ETCRAH and ETCRAL Set the number of transfers in ETCRB 4 Set each bit in DMACRA and DMACRB Set the transfer data size with the DTSZ bit Specify whether MARA is to be incremented decremented or fixed with the SAID and SAIDE bits Set the BLKE bit to 1 to select block transfer mode Specify whether the transfer source or the transfer destination is a block area with the BLKDIR bit Specify whether MAR...

Page 289: ...X X X Legend Can be specified X Cannot be specified Activation by Internal Interrupt An interrupt request selected as a DMAC activation source can be sent simultaneously to the CPU and DTC For details see section 5 Interrupt Controller With activation by an internal interrupt the DMAC accepts the request independently of the interrupt controller Consequently interrupt controller priority settings ...

Page 290: ... the DREQ pin The next transfer may not be performed if the next edge is input before transfer is completed When level sensing is selected the DMAC stands by for a transfer request while the DREQ pin is held high While the DREQ pin is held low transfers continue in succession with the bus being released each time a byte or word is transferred If the DREQ pin goes high in the middle of a transfer t...

Page 291: ...rmed from external memory to the external device and the DACK pin functions as a write strobe for the external device When using the DMAC for single address mode writing transfer is performed from the external device to external memory and the DACK pin functions as a read strobe for the external device Since there is no directional control for the external device one or other of the above single d...

Page 292: ...ination address write are performed The bus is not released in response to another bus request etc between these read and write operations As with CPU cycles DMA cycles conform to the bus controller settings ø Address bus DMAC cycle 1 word transfer RD LWR HWR Source address Destination address CPU cycle CPU cycle T1 T2 T3 T1 T2 T3 T1 T2 Figure 8 18 Example of DMA Transfer Bus Timing The address is...

Page 293: ...d DMA write DMA read DMA write Bus release Bus release Bus release Figure 8 19 Example of Short Address Mode Transfer A one byte or one word transfer is performed for one transfer request and after the transfer the bus is released While the bus is released one or more bus cycles are inserted by the CPU or DTC In the transfer end cycle the cycle in which the transfer counter reaches 0 a one state D...

Page 294: ...END HWR Bus release Last transfer cycle DMA write DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Bus release Figure 8 20 Example of Full Address Mode Cycle Steal Transfer A one byte or one word transfer is performed and after the transfer the bus is released While the bus is released one bus cycle is inserted by the CPU or DTC In the transfer end cycle the cycle in which th...

Page 295: ... in which the transfer counter reaches 0 a one state DMA dead cycle is inserted after the DMA write cycle If a request from another higher priority channel is generated after burst transfer starts that channel has to wait until the burst transfer ends If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state the DTME bit is cleared and the channel is pla...

Page 296: ...A dead DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Figure 8 22 Example of Full Address Mode Block Transfer Mode Transfer A one block transfer is performed for one transfer request and after the transfer the bus is released While the bus is released one or more bus cycles are inserted by the CPU or DTC In the transfer end cycle of each block the cycle in which the transfe...

Page 297: ...e Idle Transfer source Request Minimum of 2 cycles 1 3 2 4 6 5 7 Acceptance resumes Acceptance resumes DMA write Bus release DMA read DMA write Bus release Request Minimum of 2 cycles Transfer destination Transfer source Transfer destination Request clear period Request clear period Read Read Figure 8 23 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer DREQ pin sampling is performed...

Page 298: ...ock transfer Idle Dead Dead DMA write Bus release DMA read DMA write DMA dead Bus release Transfer source Transfer destination Request clear period Minimun of 2 cycles Request Acceptance resumes 1 block transfer Request clear period Read Read Transfer destination Idle Figure 8 24 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle with...

Page 299: ...Bus release DMA control Channel Write Idle Transfer source Bus release DMA read DMA write Bus release Request Minimum of 2 cycles 1 3 2 Minimum of 2 cycles 4 6 5 7 Acceptance resumes Acceptance resumes Transfer destination Transfer source Transfer destination Request Read Request clear period Read Request clear period Figure 8 25 Example of DREQ Level Activated Normal Mode Transfer DREQ pin sampli...

Page 300: ...s DMA dead Bus release DMA read DMA right DMA dead Bus release 1 block transfer Idle Dead Dead 1 block transfer Acceptance resumes Request Minimum of 2 cycles Transfer destination Transfer source Transfer destination Minimum of 2 cycles Read Request clear period Read Request clear period Idle Figure 8 26 Example of DREQ Level Activated Block Transfer Mode Transfer DREQ pin sampling is performed ev...

Page 301: ...ed and byte size single address mode transfer read is performed from external 8 bit 2 state access space to an external device DMA read ø Address bus DMA dead RD DACK TEND Bus release DMA read DMA read DMA read Bus release Bus release Bus release Bus release Last transfer cycle Figure 8 27 Example of Single Address Mode Byte Read Transfer ...

Page 302: ...us release Bus release Bus release Bus release Last transfer cycle Figure 8 28 Example of Single Address Mode Word Read Transfer A one byte or one word transfer is performed for one transfer request and after the transfer the bus is released While the bus is released one or more bus cycles are inserted by the CPU or DTC In the transfer end cycle the cycle in which the transfer counter reaches 0 a ...

Page 303: ...ress mode transfer write is performed from an external device to external 8 bit 2 state access space DMA write ø Address bus DMA dead HWR DACK TEND Bus release LWR DMA write DMA write DMA write Bus release Bus release Bus release Bus release Last transfer cycle Figure 8 29 Example of Single Address Mode Byte Write Transfer ...

Page 304: ...us release LWR Bus release Bus release Bus release Last transfer cycle Figure 8 30 Example of Single Address Mode Word Write Transfer A one byte or one word transfer is performed for one transfer request and after the transfer the bus is released While the bus is released one or more bus cycles are inserted by the CPU or DTC In the transfer end cycle the cycle in which the transfer counter reaches...

Page 305: ...n the DREQ pin high level has been sampled acceptance is resumed after the single cycle is completed As in 1 the DREQ pin low level is sampled on the rising edge of ø and the request is held Note In write data buffer mode bus breaks from 2 to 7 may be hidden and not visible Figure 8 31 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer DREQ pin sampling is performed every cycl...

Page 306: ...eak and activation is started in the DMAC The DMAC cycle is started Acceptance is resumed after the single cycle is completed As in 1 the DREQ pin low level is sampled on the rising edge of ø and the request is held Note In write data buffer mode bus breaks from 2 to 7 may be hidden and not visible Figure 8 32 Example of DREQ Pin Low Level Activated Single Address Mode Transfer DREQ pin sampling i...

Page 307: ...t from the TEND pin if the bus cycle in which a low level is to be output is an external bus cycle However a low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle and an external write cycle is executed in parallel with this cycle Figure 8 33 shows an example of burst mode transfer from on chip RAM to external mem...

Page 308: ...erned has ended and starts the next operation Therefore DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer 8 5 13 DMAC Multi Channel Operation The DMAC channel priority order is channel 0 channel 1 and channel A channel B Table 8 13 summarizes the priority order for DMAC channels Table 8 13 DMAC Channel Priority Order Short Address Mode Full Ad...

Page 309: ... not be changed until the end of the transfer Figure 8 35 shows a transfer example in which transfer requests are issued simultaneously for channels 0A 0B and 1 DMA read DMA write DMA read DMA write DMA read DMA write DMA read ø Address bus RD HWR LWR DMA control Channel 0A Channel 0B Channel 1 Idle Write Idle Read Write Idle Read Write Read Request clear Request hold Request hold Request clear Re...

Page 310: ... successive read and write cycles such as in burst transfer or block transfer a refresh or external bus released state may be inserted after a write cycle Since the DTC has a lower priority than the DMAC the DTC does not operate until the DMAC releases the bus When DMA cycle reads or writes are accesses to on chip memory or internal I O registers these DMA cycles can be executed at the same time a...

Page 311: ...ontinues transfer on completion of the 1 byte or 1 word transfer in progress then releases the bus which passes to the CPU The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again Figure 8 36 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer Resumption of transfer on ...

Page 312: ...ain In full address mode the same applies to the DTME bit Figure 8 37 shows the procedure for forcibly terminating DMAC operation by software Forced termination of DMAC Clear DTE bit to 0 Forced termination 1 1 Clear the DTE bit in DMABCRL to 0 If you want to prevent interrupt generation after forced termination of DMAC operation clear the DTIE bit to 0 at the same time Figure 8 37 Example of Proc...

Page 313: ...e Clearing full address mode Stop the channel Initialize DMACR Clear FAE bit to 0 Initialization operation halted 1 2 3 1 Clear both the DTE bit and the DTME bit in DMABCRL to 0 or wait until the transfer ends and the DTE bit is cleared to 0 then clear the DTME bit to 0 Also clear the corresponding DTIE bit to 0 at the same time 2 Clear all bits in DMACRA and DMACRB to 0 3 Clear the FAE bit in DMA...

Page 314: ...ing or disabling of each interrupt source is set by means of the DTIE bit for the corresponding channel in DMABCR and interrupts from each source are sent to the interrupt controller independently The relative priority of transfer end interrupts on each channel is decided by the interrupt controller as shown in table 8 14 Figure 8 39 shows a block diagram of a transfer end transfer break interrupt...

Page 315: ...counter ETCR operation decremented in block transfer mode 2 Transfer destination address register MAR operation incremented decremented fixed 2 Transfer destination address register MAR operation incremented decremented fixed Block transfer counter ETCR operation decremented in last transfer cycle of a block in block transfer mode 3 Transfer address register MAR restore operation in block or repea...

Page 316: ...hen the DMAC clock stops DMAC register accesses can no longer be made Since the following DMAC register settings are valid even in the module stop state they should be invalidated if necessary before a module stop Transfer end suspend interrupt DTE 0 and DTIE 1 TEND pin enable TEE 1 DACK pin enable FAE 0 and SAE 1 Medium Speed Mode When the DTA bit is 0 internal interrupt signals specified as DMAC...

Page 317: ...b Write Data Buffer Function and DMAC Operation Timing The DMAC can start its next operation during external access using the write data buffer function Consequently the DREQ pin sampling timing TEND output timing etc are different from the case in which the write data buffer function is disabled Also internal bus cycles maybe hidden and not visible c Write Data Buffer Function and TEND Output A l...

Page 318: ...sible and switches to 3 3 Activation request disabled state Waits for detection of a high level on the DREQ pin and switches to 1 After DMAC transfer is enabled a transition is made to 1 Thus initial activation after transfer is enabled is performed by detection of a low level Activation Source Acceptance At the start of activation source acceptance a low level is detected in both DREQ pin falling...

Page 319: ... enabled use exclusive handling of transfer end interrupts and perform DMABCR control bit operations exclusively Note in particular that in cases where multiple interrupts are generated between reading and writing of DMABCR and a DMABCR operation is performed during new interrupt handling the DMABCR write data in the original interrupt handling routine will be incorrect and the write may invalidat...

Page 320: ...crementing decrementing and fixing of source and destination addresses can be selected Direct specification of 16 Mbyte address space possible 24 bit transfer source and destination addresses can be specified Transfer can be set in byte or word units A CPU interrupt can be requested for the interrupt that activated the DTC An interrupt request can be issued to the CPU after one data transfer ends ...

Page 321: ...st be set to 1 Interrupt request Interrupt controller DTC Internal address bus DTC service request Control logic Register information MRA MRB CRA CRB DAR SAR CPU interrupt request On chip RAM Internal data bus Legend MRA MRB CRA CRB SAR DAR DTCERA to DTCERF DTCERI DTVECR DTCERA to DTCERF DTCERI DTVECR DTC mode registers A and B DTC transfer count registers A and B DTC source address register DTC d...

Page 322: ...ansfer count register A CRA 2 Undefined 3 DTC transfer count register B CRB 2 Undefined 3 DTC enable registers DTCER R W H 00 H FE16 to H FE1E DTC vector register DTVECR R W H 00 H FE1F Module stop control register MSTPCRA R W H 3F H FDE8 Notes 1 Lower 16 bits of the address 2 Registers within the DTC cannot be read or written to directly 3 Register information is located in on chip RAM addresses ...

Page 323: ...nted decremented or left fixed after a data transfer Bit 7 Bit 6 SM1 SM0 Description 0 SAR is fixed 1 0 SAR is incremented after a transfer by 1 when Sz 0 by 2 when Sz 1 1 SAR is decremented after a transfer by 1 when Sz 0 by 2 when Sz 1 Bits 5 and 4 Destination Address Mode 1 and 0 DM1 DM0 These bits specify whether DAR is to be incremented decremented or left fixed after a data transfer Bit 5 Bi...

Page 324: ... DTS Specifies whether the source side or the destination side is set to be a repeat area or block area in repeat mode or block transfer mode Bit 1 DTS Description 0 Destination side is repeat area or block area 1 Source side is repeat area or block area Bit 0 DTC Data Transfer Size Sz Specifies the size of data to be transferred Bit 0 Sz Description 0 Byte size transfer 1 Word size transfer ...

Page 325: ...DTCER is not performed Bit 7 CHNE Description 0 End of DTC data transfer activation waiting state is entered 1 DTC chain transfer new register information is read then data is transferred Bit 6 DTC Interrupt Select DISEL Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer Bit 6 DISEL Description 0 After a data transfer ends the CPU interrupt is disabled un...

Page 326: ...DTC Transfer Count Register A CRA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CRAH CRAL Bit Initial value Unde fined R W Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined Unde fined CRA is a 16 bit register that designates the number of times data is to be transferred by the DTC In normal mode the ent...

Page 327: ...en 8 bit readable writable registers DTCERA to DTCERF and DTCERI with bits corresponding to the interrupt sources that can control enabling and disabling of DTC activation These bits enable or disable DTC service for the corresponding interrupt sources The DTC enable registers are initialized to H 00 by a reset and in hardware standby mode Bit n DTC Activation Enable DTCEn Bit n DTCEn Description ...

Page 328: ... H 00 by a reset and in hardware standby mode Bit 7 DTC Software Activation Enable SWDTE Enables or disables DTC activation by software Bit 7 SWDTE Description 0 DTC software activation is disabled Initial value Clearing conditions When the DISEL bit is 0 and the specified number of transfers have not ended When 0 s written to the DISEL bit after a software activated data transfer end interrupt SW...

Page 329: ...RA is set to 1 the DTC operation stops at the end of the bus cycle and a transition is made to module stop mode However 1 cannot be written in the MSTPA6 bit while the DTC is operating For details see section 24 5 Module Stop Mode MSTPCRA is initialized to H 3F by a reset and in hardware standby mode It is not initialized in software standby mode Bit 6 Module Stop MSTPA6 Specifies the DTC module s...

Page 330: ... in memory makes it possible to transfer data over any required number of channels Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation Figure 9 2 shows a flowchart of DTC operation Start Read DTC vector Next transfer Read register information Data transfer Write register information Clear an activation flag CHNE 1 End No No Yes Yes Transfer Counter...

Page 331: ... request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 Up to 65 536 transfers possible Repeat mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 After the specified number of transfers 1 to 256 the initial state resumes and operation continues Block transfer mode One transfer request transfer...

Page 332: ... Source When the DISEL Bit Is 0 and the Specified Number of Transfers Have Not Ended When the DISEL Bit Is 1 or when the Specified Number of Transfers Have Ended Software activation The SWDTE bit is cleared to 0 The SWDTE bit remains set to 1 An interrupt is issued to the CPU Interrupt activation The corresponding DTCER bit remains set to 1 The activation source flag is cleared to 0 The correspond...

Page 333: ...VECR is H 10 the vector address is H 0420 The DTC reads the start address of the register information from the vector address set for each activation source and then reads the register information from that start address The register information can be placed at predetermined addresses in the on chip RAM The start address of the register information should be an integral multiple of four The confi...

Page 334: ... H 042C DTCEA1 IRQ7 23 H 042E DTCEA0 ADI A D conversion end A D 28 H 0438 DTCEB6 TGI0A GR0A compare match input capture TPU channel 0 32 H 0440 DTCEB5 TGI0B GR0B compare match input capture 33 H 0442 DTCEB4 TGI0C GR0C compare match input capture 34 H 0444 DTCEB3 TGI0D GR0D compare match input capture 35 H 0446 DTCEB2 TGI1A GR1A compare match input capture TPU channel 1 40 H 0450 DTCEB1 TGI1B GR1B ...

Page 335: ...nput capture 61 H 047A DTCED4 CMIA0 compare match A0 8 bit timer 64 H 0480 DTCED3 CMIB0 compare match B0 channel 0 65 H 0482 DTCED2 CMIA1 compare match A1 8 bit timer 68 H 0488 DTCED1 CMIB1 compare match B1 channel 1 69 H 048A DTCED0 DEND0A channel 0 channel 0A transfer end DMAC 72 H 0490 DTCEE7 DEND0B channel 0B transfer end 73 H 0492 DTCEE6 DEND1A channel 1 channel 1A transfer end 74 H 0494 DTCE...

Page 336: ...el 3 97 H 04C2 DTCEF2 IICI0 1 byte transmit reception complete IIC channel 0 option 100 H 04C8 DTCEF1 IICI1 1 byte transmit reception complete IIC channel 1 option 102 H 04CC DTCEF0 RXI3 reception complete 3 SCI channel 3 121 H 04F2 DTCEI7 TXI3 transmit data empty 3 122 H 04F4 DTCEI6 RXI4 reception complete 4 SCI channel 4 125 H 04FA DTCEI5 TXI4 transmit data empty 4 126 H 04FC DTCEI4 Low Note DTC...

Page 337: ...ents of the vector address In the case of chain transfer register information should be located in consecutive areas Locate the register information in the on chip RAM addresses H FFEBC0 to H FFEFBF Register information start address Chain transfer Register information for 2nd transfer in chain transfer MRA SAR MRB DAR CRA CRB 4 bytes Lower address CRA CRB Register information MRA 0 1 2 3 SAR MRB ...

Page 338: ...ster information in normal mode and figure 9 6 shows memory mapping in normal mode Table 9 5 Register Information in Normal Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register A CRA Designates transfer count DTC transfer count register B CRB Not used Transfer SAR DA...

Page 339: ...terrupts cannot be requested when DISEL 0 Table 9 6 lists the register information in repeat mode and figure 9 7 shows memory mapping in repeat mode Table 9 6 Register Information in Repeat Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destination address register DAR Designates destination address DTC transfer count register AH CRAH Holds number of ...

Page 340: ...xed From 1 to 65 536 transfers can be specified Once the specified number of transfers have ended a CPU interrupt is requested Table 9 7 lists the register information in block transfer mode and figure 9 8 shows memory mapping in block transfer mode Table 9 7 Register Information in Block Transfer Mode Name Abbreviation Function DTC source address register SAR Designates source address DTC destina...

Page 341: ...316 Transfer SAR or DAR DAR or SAR Block area First block Nth block Figure 9 8 Memory Mapping in Block Transfer Mode ...

Page 342: ...memory map for chain transfer Source Source Destination Destination DTC vector address Register information start address Register information CHNE 1 Register information CHNE 0 Figure 9 9 Chain Transfer Memory Map In the case of transfer with CHNE set to 1 an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1 and the i...

Page 343: ...on read Transfer information write Data transfer Read Write ø Figure 9 10 DTC Operation Timing Example in Normal Mode or Repeat Mode Read Write Read Write Data transfer Transfer information write Transfer information read Vector read ø DTC activation request DTC request Address Figure 9 11 DTC Operation Timing Example of Block Transfer Mode with Block Size of 2 ...

Page 344: ...ing Example of Chain Transfer 9 3 10 Number of DTC Execution States Table 9 8 lists execution statuses for a single DTC data transfer and table 9 9 shows the number of states required for each execution status Table 9 8 DTC Execution Statuses Mode Vector Read I Register Information Read Write J Data Read K Data Write L Internal Operations M Normal 1 6 1 1 3 Repeat 1 6 1 1 3 Block transfer 1 6 N N ...

Page 345: ... 3 m Word data write SL 1 1 4 2 4 6 2m 2 3 m Internal operation SM 1 The number of execution states is calculated from the formula below Note that Σ means the sum of all transfers activated by one activation event the number in which the CHNE bit is set to 1 plus 1 Number of execution states I SI Σ J SJ K SK L SL M SM For example when the DTC vector address table is located in on chip ROM normal m...

Page 346: ... to 0 and a CPU interrupt is requested If the DTC is to continue transferring data set the DTCE bit to 1 Activation by Software The procedure for using the DTC with software activation is as follows 1 Set the MRA MRB SAR DAR CRA and CRB register information in the on chip RAM 2 Set the start address of the register information in the DTC vector address 3 Check that the SWDTE bit is 0 4 Write 1 to ...

Page 347: ...n DTCER to 1 4 Set the SCI to the appropriate receive mode Set the RIE bit in SCR to 1 to enable the reception complete RXI interrupt Since the generation of a receive error during the SCI reception operation will disable subsequent reception the CPU should be enabled to accept receive error interrupts 5 Each time reception of one byte of data ends on the SCI the RDRF flag in SSR is set to 1 an RX...

Page 348: ...ddress DM1 DM0 0 normal mode MD1 MD0 0 and word size Sz 1 Set the data table start address in SAR the TGRA address in DAR and the data table size in CRA CRB can be set to any value 3 Locate the TPU transfer register information consecutively after the NDR transfer register information 4 Set the start address of the NDR transfer register information to the DTC vector address 5 Set the bit correspon...

Page 349: ...t 1 H 0001 in CRB 2 Set the start address of the register information at the DTC vector address H 04C0 3 Check that the SWDTE bit in DTVECR is 0 Check that there is currently no transfer activated by software 4 Write 1 to the SWDTE bit and the vector number H 60 to DTVECR The write data is H E0 5 Read DTVECR again and check that it is set to the vector number H 60 If it is not this indicates that ...

Page 350: ...ivated by software an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1 9 5 Usage Notes Module Stop When the MSTPA6 bit in MSTPCRA is set to 1 the DTC clock stops and the DTC enters the module stop state However 1 cannot be written in the MSTPA6 bit while the DTC is operating On Chip RAM The MRA MRB SAR DAR CRA and CRB register...

Page 351: ...uilt in pull up MOS function and in addition to DR and DDR have a MOS input pull up control register PCR to control the on off state of MOS input pull up Ports 3 and A to C include an open drain control register ODR that controls the on off state of the output buffer PMOS When ports 10 to 13 70 to 73 and A to G are used as the output pins for expanded bus control signals they can drive one TTL loa...

Page 352: ...g as DMA controller output pins DACK0 DACK1 TPU I O pins TCLKA TCLKB TCLKC TCLKD TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 PPG output pins PO15 to PO8 interrupt input pins IRQ0 IRQ1 and 14 bit PWM output pins PWM2 PWM3 Port 3 8 bit I O port Open drain output capability Schmitt triggered input P35 P32 P37 TxD4 P36 RxD4 P35 SCK1 SCK4 SCL0 IRQ5 P34 RxD1 SDA0 P33 TxD1 SCL1 P32 SCK0 SDA1 ...

Page 353: ... as 8 bit timer I O pins TMRI01 TMCI01 TMRI23 TMCI23 TMO0 TMO1 TMO2 TMO3 DMAC I O pins DREQ0 TEND0 DREQ1 TEND1 the IIC input pin SYNCI SCI I O pins SCK3 RxD3 TxD3 and the manual reset input pin MRES Port 9 8 bit input port P97 AN15 DA3 P96 AN14 DA2 P95 AN13 P94 AN12 P93 AN11 P92 AN10 P91 AN9 P90 AN8 8 bit input port also functioning as A D converter analog inputs AN15 to AN8 and D A converter anal...

Page 354: ...OCB3 TIIOCA3 Port C 8 bit I O port Built in MOS input pull up Open drain output capability PC7 A7 PWM1 PC6 A6 PWM0 PC5 A5 PC4 A4 PC3 A3 PC2 A2 PC1 A1 PC0 A0 8 bit I O port also functioning as 14 bit PWM channel 1 and 0 output pins PWM1 PWM0 and address outputs A7 to A0 8 bit I O port also function ing as 14 bit PWM channel 1 and 0 output pins PWM1 PWM0 Port D 8 bit I O port Built in MOS input pull...

Page 355: ...BREQOE 0 WAIT input When WAITE 0 and BREQOE 1 BREQO input When RMTS2 to RMTS0 B 001 to B 011 CW2 0 and LCASS 0 LCAS output I O port PF1 BACK BUZZ PF0 BREQ IRQ2 When BRLE 0 after reset I O port When BRLE 1 BREQ input BACK output BUZZ output IRQ2 input BUZZ output IRQ2 input I O port Port G 5 bit I O port PG4 CS0 When DDR 0 1 input port When DDR 1 2 CS0 output I O port PG3 CS1 PG2 CS2 PG1 CS3 OE IRQ...

Page 356: ...15 I O PO13 output TIOCB1 I O TCLKC input P14 I O PO12 output TIOCA1 I O IRQ0 input P13 I O PO11 output TIOCD0 I O TCLKB input A23 output P12 I O PO10 output TIOCC0 I O TCLKA input A22 output P11 I O PO9 output TIOCB0 I O DACK1 output A21 output P10 I O PO8 output TIOCA0 I O DACK0 output A20 output Port 1 Port 1 pins Pin functions in modes 4 to 6 P17 I O PO15 output TIOCB2 I O PWM3 output TCLKD in...

Page 357: ...t is an undefined value will be read Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin while clearing the bit to 0 makes the pin an input pin P1DDR is initialized to H 00 by a power on reset and in hardware standby mode It retains its prior state by a manual reset or in software standby mode Because PPG TPU and DMAC are initialized at a manual reset pin states are determine...

Page 358: ...utput data for the port 1 pins P17 to P10 must always be performed on P1DR If a port 1 read is performed while P1DDR bits are set to 1 the P1DR values are read If a port 1 read is performed while P1DDR bits are cleared to 0 the pin states are read After a power on reset and in hardware standby mode PORT1 contents are determined by the pin states as P1DDR and P1DR are initialized PORT1 retains its ...

Page 359: ...s IOB3 to IOB0 in TIOR2 and bits CCLR1 and CCLR0 in TCR2 bits TPSC2 to TPSC0 in TCR0 and TCR5 OEB bit in DACR3 bit NDER15 in NDERH and bit P17DDR TPU Channel 2 Setting Table Below 1 Table Below 2 OEB 0 0 0 1 P17DDR 0 1 1 NDER15 0 1 Pin function TIOCB2 output P17 input P17 output PO15 output PWM3 output TIOCB2 input 1 TCLKD input 2 Notes 1 TIOCB2 input when MD3 to MD0 B 0000 or B 01xx and IOB3 1 2 ...

Page 360: ...elow 1 Table Below 2 OEA 0 0 0 1 P16DDR 0 1 1 NDER14 0 1 Pin function TIOCA2 output P16 input P16 output PO14 output PWM2 output TIOCA2 input 1 IRQ1 input TPU Channel 2 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 01xx B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR1 CCLR0 Other than B 01 B 01 Output function Output compare output P...

Page 361: ...B1 output P15 input P15 output PO13 output TIOCB1 input 1 TCLKC input 2 Notes 1 TIOCB1 input when MD3 to MD0 B 0000 or B 01xx and IOB3 to IOB0 B 10xx 2 TCLKC input when the setting for either TCR0 or TCR2 is TPSC2 to TPSC0 B 110 or when the setting for either TCR4 or TCR5 is TPSC2 to TPSC0 B 101 TCLKC input when channels 2 and 4 are set to phase counting mode TPU Channel 1 Setting 2 1 2 2 1 2 MD3 ...

Page 362: ...low 2 P14DDR 0 1 1 NDER12 0 1 Pin function TIOCA1 output P14 input P14 output PO12 output TIOCA1 input 1 IRQ0 input TPU Channel 1 Setting 2 1 2 1 1 2 MD3 to MD0 B 0000 B 01xx B 001x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 Other than B xx00 CCLR1 CCLR0 Other than B 01 B 01 Output function Output compare output PWM mode 1 output 2 PW...

Page 363: ...E3 to AE0 B 0000 to B 1110 B 1111 TPU Channel 0 Setting Table Below 1 Table Below 2 P13DDR 0 1 1 NDER11 0 1 Pin function TIOCD0 output P13 input P13 output PO11 output A23 output TIOCD0 input 1 TCLKB input 2 Operating mode Mode 7 AE3 to AE0 TPU Channel 0 Setting Table Below 1 Table Below 2 P13DDR 0 1 1 NDER11 0 1 Pin function TIOCD0 output P13 input P13 output PO11 output TIOCD0 input 1 TCLKB inpu...

Page 364: ...Channel 0 Setting 2 1 2 2 1 2 A23 cont MD3 to MD0 B 0000 B 0010 B 0011 IOD3 to IOD0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR2 to CCLR0 Other than B 110 B 110 Output function Output compare output PWM mode 2 output x Don t care ...

Page 365: ... TCR0 to TCR5 bits AE3 to AE0 in PFCR bit NDER10 in NDERH and bit P12DDR Operating mode Modes 4 to 6 AE3 to AE0 B 0000 to B 1110 B 1111 TPU Channel 0 Setting Table Below 1 Table Below 2 P12DDR 0 1 1 NDER10 0 1 Pin function TIOCC0 output P12 input P12 output PO10 output A22 output TIOCC0 input 1 TCLKA input 2 Operating mode Mode 7 AE3 to AE0 TPU Channel 0 Setting Table Below 1 Table Below 2 P12DDR ...

Page 366: ... xx00 CCLR2 to CCLR0 Other than B 101 B 101 Output function Output compare output PWM mode 1 output 3 PWM mode 2 output x Don t care Notes 1 TIOCC0 input when MD3 to MD0 B 0000 and IOC3 to IOC0 B 10xx 2 TCLKA input when the setting for TCR0 to TCR5 is TPSC2 to TPSC0 B 100 TCLKA input when channels 1 and 5 are set to phase counting mode 3 TIOCD0 output is disabled When BFA 1 or BFB 1 in TMDR0 outpu...

Page 367: ...11DDR Operating mode Modes 4 to 6 AE3 to AE0 B 0000 to B 1101 B 1110 to B 1111 SAE1 0 1 TPU Channel 0 Setting Table Below 1 Table Below 2 P11DDR 0 1 1 NDER9 0 1 Pin function TIOCB0 output P11 input P11 output PO9 output DACK1 output A21 output TIOCB0 input 1 Operating mode Mode 7 AE3 to AE0 SAE1 0 1 TPU Channel 0 Setting Table Below 1 Table Below 2 P11DDR 0 1 1 NDER9 0 1 Pin function TIOCB0 output...

Page 368: ...cont TPU Channel 0 Setting 2 1 2 2 1 2 MD3 to MD0 B 0000 B 0010 B 0011 IOB3 to IOB0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR2 to CCLR0 Other than B 010 B 010 Output function Output compare output PWM mode 2 output x Don t care ...

Page 369: ...it NDER8 in NDERH SAE0 bit in DMABCRH and bit P10DDR Operating mode Modes 4 to 6 AE3 to AE0 B 0000 to B 1110 B 1101 to B 1111 SAE0 0 1 TPU Channel 0 Setting Table Below 1 Table Below 2 P10DDR 0 1 1 NDER8 0 1 Pin function TIOCA0 output P10 input P10 output PO8 output DACK0 output A20 output TIOCA0 input 1 Operating mode Mode 7 AE3 to AE0 SAE0 0 1 TPU Channel 0 Setting Table Below 1 Table Below 2 P1...

Page 370: ...x B 0010 B 0011 IOA3 to IOA0 B 0000 B 0100 B 1xxx B 0001 to B 0011 B 0101 to B 0111 B xx00 Other than B xx00 CCLR2 to CCLR0 Other than B 001 B 001 Output function Output compare output PWM mode 1 output 2 PWM mode 2 output x Don t care Notes 1 TIOCA0 input when MD3 to MD0 B 0000 and IOA3 to IOA0 B 10xx 2 TIOCB0 output is disabled ...

Page 371: ...put input output input output input output input output TxD4 output RxD4 input SCK1 input output RxD1 input SDA0 input output TxD1 input SCL1 input output SCK0 input output SDA1 input output IRQ4 input RxD0 input IrRxD input TxD0 output IrTxD output Port 3 pins Port 3 Figure 10 2 Port 3 Pin Functions 10 3 2 Register Configuration Table 10 4 shows the configuration of port 3 registers Table 10 4 Po...

Page 372: ...lized to H 00 by a power on reset and in hardware standby mode The previous state is maintained by a manual reset and in software standby mode SCI and IIC are initialized so the pin state is determined by the specification of P3DDR and P3DR Port 3 Data Register P3DR 7 P37DR 0 R W Bit Initial value R W 6 P36DR 0 R W 5 P35DR 0 R W 4 P34DR 0 R W 3 P33DR 0 R W 2 P32DR 0 R W 1 P31DR 0 R W 0 P30DR 0 R W...

Page 373: ...alized by a power on reset and in hardware standby mode so PORT3 is determined by the state of the pins The previous state is maintained by a manual reset and in software standby mode Port 3 Open Drain Control Register P3ODR 7 P37DDR 0 W Bit Initial value R W 6 P36DDR 0 W 5 P35DDR 0 W 4 P34DDR 0 W 3 P33DDR 0 W 2 P32DDR 0 W 1 P31DDR 0 W 0 P30DDR 0 W P3ODR is an 8 bit readable writable register whic...

Page 374: ... P36 input pin P36 output pin RxD4 input pin Note When P36ODR 1 it becomes NMOS open drain output P35 SCK1 SCK4 SCL0 IRQ5 Switches as follows according to combinations of ICCR0 ICE bit of IIC0 SMR C A bit of SCI1 or SCI4 SCR CKE0 and CKE1 bits and the P35DDR bit When used as a SCL0 I O pin always be sure to clear the following bits to 0 SMR C A bits of SCI1 or SCI4 and SCR CKE0 and CKE1 bits Do no...

Page 375: ...mat becomes NMOS open drain output enabling direct bus driving ICE 0 1 TE 0 1 P33DDR 0 1 Pin function P33 input pin P33 output pin TxD1 output pin SCL1 I O pin Note When P33ODR 1 it becomes NMOS open drain output P32 SCK0 SDA1 IRQ4 Switches as follows according to combinations of ICCR1 ICE bit of IIC1 SMR C A bit of SCI0 SCR CKE0 and CKE1 bits and the P32DDR bit If using as an SDA1 input pin alway...

Page 376: ...R 0 1 Pin function P31 input pin P31 output pin RxD0 IrRxD input pin Note When P31ODR 1 it becomes NMOS open drain output P30 TxD0 IrTxD Switches as follows according to combinations of SCR TE bit of SCI0 and the P30DDR bit TE 0 1 P30DDR 0 1 Pin function P30 input pin P30 output pin TxD0 IrTxD output pin Note When P30ODR 1 it becomes NMOS open drain output ...

Page 377: ...log output pins DA0 DA1 Port 4 pin functions are the same in all operating modes Figure 10 3 shows the port 4 pin configuration P47 P46 P45 P44 P43 P42 P41 P40 input input input input input input input input AN7 input DA1 output AN6 input DA0 output AN5 input AN4 input AN3 input AN2 input AN1 input AN0 input Port 4 pins Port 4 Figure 10 3 Port 4 Pin Functions ...

Page 378: ... Address Port 4 register PORT4 R Undefined H FFB3 Note Lower 16 bits of the address Port 4 Register PORT4 The pin states are always read when a port 4 read is performed Bit 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 Initial value R W R R R R R R R R Note Determined by state of pins P47 to P40 10 4 3 Pin Functions Port 4 pins also function as A D converter analog input pins AN0 to AN7 and D A ...

Page 379: ...nput output input output TxD3 RxD3 TMO3 SCK3 TMO2 MRES TMO1 TEND1 CS7 TMO0 TEND0 CS6 SYNCI TMRI23 TMCI23 DREQ1 CS5 TMRI01 TMCI01 DREQ0 CS4 Port 6 pins Pins Functions for Modes 4 to 6 Modes 7 Pin Functions Port 7 TxD3 output RxD3 input TMO3 output SCK3 input output TMO2 output MRES input TMO1 output TEND1 output CS7 output TMO0 output TEND0 output CS6 output SYNCI input TMRI23 input TMCI23 input DR...

Page 380: ...0 W 5 P75DDR 0 W 4 P74DDR 0 W 3 P73DDR 0 W 2 P72DDR 0 W 1 P71DDR 0 W 0 P70DDR 0 W P7DDR is an 8 bit write dedicated register which specifies the I O for each port 7 pin by bit Read is disenabled If a read is carried out undefined values are read out By setting P7DDR to 1 the corresponding port 7 pins become output and by clearing to 0 they become input P7DDR is initialized to H 00 by a power on re...

Page 381: ...nitial value R W 6 P76 R 5 P75 R 4 P74 R 3 P73 R 2 P72 R 1 P71 R 0 P70 R Note Determined by the state of pins P77 to P70 PORT7 is an 8 bit read dedicated register which reflects the state of pins Write is disenabled Always carry out writing off output data of port 7 pins P77 to P70 to P7DR without fail When P7DDR is set to 1 if port 7 is read the values of P7DR are read When P7DDR is cleared to 0 ...

Page 382: ...llows according to combinations of SCR TE bit of SCI3 and the P77DDR bit TE 0 1 P77DDR 0 1 Pin function P77 input pin P77 output pin TxD3 output pin P76 RxD3 Switches as follows according to combinations of SCR RE bit of SCI3 and the P76DDR bit RE 0 1 P76DDR 0 1 Pin function P76 input pin P76 output pin RxD3 I O pin P75 TMO3 SCK3 Switches as follows according to combinations of SMR C A bit of SCI3...

Page 383: ...rating Mode Modes 4 to 6 Mode 7 TEE1 0 1 0 1 OS3 to OS0 All 0 Any is 1 All 0 Any is 1 P73DDR 0 1 0 1 Pin function P73 input pin CS7 output pin TMO1 output TEND1 output P73 input pin P73 output pin TMO1 output TEND1 output P72 TMO0 TEND0 CS6 Switches as follows according to combinations of operating mode and DMATCR TEE0 bit of DMAC OS3 to OS0 bits of 8 bit timer TCSR0 and the P72DDR bit SYNCI Opera...

Page 384: ...0 1 Pin function P71 input Pin CS5 output P71 input pin P71 output pin DREQ0 TMRI23 TMCI23 input DREQ0 TMRI23 TMCI23 input P70 TMRI01 Switches as follows according to operating mode and P70DDR TMCI01 DREQ0 CS4 Operating Mode Modes 4 to 6 Mode 7 P70DDR 0 1 0 1 Pin function P70 input pin CS4 output P70 input pin P70 output pin DREQ0 TMRI01 TMCI01 input DREQ0 TMRI01 TMCI01 input ...

Page 385: ...g output pins DA2 DA3 Port 9 pin functions are the same in all operating modes Figure 10 5 shows the port 9 pin configuration P97 P96 P95 P94 P93 P92 P91 P90 input input input input input input input input AN15 input DA3 output AN14 input DA2 output AN13 input AN12 input AN11 input AN10 input AN9 input AN8 input Port 9 pins Port 9 Figure 10 5 Port 9 Pin Functions ...

Page 386: ...ort 9 register PORT9 R Undefined H FFB8 Note Lower 16 bits of the address Port 9 Register PORT9 The pin states are always read when a port 9 read is performed Bit 7 6 5 4 3 2 1 0 P97 P96 P95 P94 P93 P92 P91 P90 Initial value R W R R R R R R R R Note Determined by state of pins P97 to P90 10 6 3 Pin Functions Port 9 pins are multipurpose pins which function as A D converter analog input pins AN8 to...

Page 387: ...nput pull up function that can be controlled by software Figure 10 6 shows the port A pin configuration PA3 A19 SCK2 PA2 A18 RxD2 PA1 A17 TxD2 PA0 A16 Port A pins Pin functions in mode 7 PA3 I O A19 output SCK2 I O PA2 I O A18 output RxD2 input PA1 I O A17 output TxD2 output PA0 I O A16 output Pin functions in modes 4 to 6 PA3 I O SCK2 output PA2 I O RxD2 input PA1 I O TxD2 output PA0 I O Port A F...

Page 388: ...R cannot be read if it is an undefined value will be read Bits 7 and 6 are reserved they return an undetermined value if read PADDR is initialized to H 0 bits 3 to 0 by a power on reset and in hardware standby mode It retains its prior state by a manual reset or in software standby mode The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high ...

Page 389: ...PA0 Initial value Undefined Undefined Undefined Undefined R W R R R R Note Determined by state of pins PA3 to PA0 PORTA is an 8 bit read only register that shows the pin states It cannot be written to Writing of output data for the port A pins PA7 to PA0 must always be performed on PADR Bits 7 to 4 are reserved they return an undetermined value if read and cannot be modified If a port A read is pe...

Page 390: ...1 turns on the MOS input pull up for that pin PAPCR is initialized by a manual reset or to H 0 bits 3 to 0 by a power on reset and in hardware standby mode It retains its prior state in software standby mode Port A Open Drain Control Register PAODR Bit 7 6 5 4 3 2 1 0 PA3ODR PA2ODR PA1ODR PA0ODR Initial value Undefined Undefined Undefined Undefined 0 0 0 0 R W R W R W R W R W PAODR is an 8 bit rea...

Page 391: ...put can be specified for each pin on an individual bit basis Setting a PADDR bit to 1 makes the corresponding port A pin an output port while clearing the bit to 0 makes the pin an input port Port A pin functions are shown in figure 10 8 PA3 I O SCK2 I O PA2 I O RxD2 input PA1 I O TxD2 output PA0 I O Port A Figure 10 8 Port A Pin Functions Mode 7 10 7 4 MOS Input Pull Up Function Port A has a buil...

Page 392: ...nd in hardware standby mode The prior state is retained by a manual reset or in software standby mode Table 10 11 summarizes the MOS input pull up states Table 10 11 MOS Input Pull Up States Port A Pin States Power On Reset Hardware Standby Mode Manual Reset Software Standby Mode In Other Operations Address output or SCI output OFF OFF OFF OFF OFF Other than above ON OFF ON OFF ON OFF Legend OFF M...

Page 393: ...4 TIOCA5 PB5 A13 TIOCB4 PB4 A12 TIOCA4 PB3 A11 TIOCD3 PB2 A10 TIOCC3 PB1 A9 TIOCB3 PB0 A8 TIOCA3 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 I O I O I O I O I O I O I O I O A15 A14 A13 A12 A11 A10 A9 A8 output TIOCB5 I O output TIOCA5 I O output TIOCB4 I O output TIOCA4 I O output TIOCD3 I O output TIOCC3 I O output TIOCB3 I O output TIOCA3 I O Port B pins Pin functions in mode 7 Pin functions in modes 4 to 6...

Page 394: ...tput for the pins of port B PBDDR cannot be read if it is an undefined value will be read PBDDR is initialized to H 00 by a power on reset and in hardware standby mode It retains its prior state by a manual reset or in software standby mode The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high impedance when a transition is made to software...

Page 395: ...2 1 0 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 Initial value R W R R R R R R R R Note Determined by state of pins PB7 to PB0 PORTB is an 8 bit read only register that shows the pin states It cannot be written to Writing of output data for the port B pins PB7 to PB0 must always be performed on PBDR If a port B read is performed while PBDDR bits are set to 1 the PBDR values are read If a port B read is perfo...

Page 396: ... 1 turns on the MOS input pull up for that pin PBPCR is initialized to H 00 by a power on reset and in hardware standby mode It retains its prior state by a manual reset or in software standby mode Port B Open Drain Control Register PBODR Bit 7 6 5 4 3 2 1 0 PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W PBODR is an 8 bit r...

Page 397: ...t TIOCC3 I O I O A9 output TIOCB3 I O I O A8 output TIOCA3 I O Figure 10 10 Port B Pin Functions Modes 4 to 6 Mode 7 In mode 7 port B pins function as I O ports and TPU I O pins TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 and TIOCB5 Input or output can be specified for each pin on an individual bit basis Setting a PBDDR bit to 1 makes the corresponding port B pin an output port while clearing...

Page 398: ...s in the TPU s TIOR and in DDR setting the corresponding PBPCR bit to 1 turns on the MOS input pull up for that pin The MOS input pull up function is in the off state after a power on reset and in hardware standby mode The prior state is retained by a manual reset or in software standby mode Table 10 13 summarizes the MOS input pull up states Table 10 13 MOS Input Pull Up States Port B Pin States ...

Page 399: ...software Figure 10 12 shows the port C pin configuration PC7 A7 PWM1 PC6 A6 PWM0 PC5 A5 PC4 A4 PC3 A3 PC2 A2 PC1 A1 PC0 A0 Port C Port C pins Pin functions in mode 7 A7 A6 A5 A4 A3 A2 A1 A0 output output output output output output output output Pin functions in modes 4 to 6 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 input output PWM1 output input output PWM0 output input output input output input output inp...

Page 400: ...he individual bits of which specify input or output for the pins of port C PCDDR cannot be read if it is an undefined value will be read PCDDR is initialized to H 00 by a power on reset and in hardware standby mode It retains its prior state by a manual reset or in software standby mode The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high ...

Page 401: ...C6 PC5 PC4 PC3 PC2 PC1 PC0 Initial value R W R R R R R R R R Note Determined by state of pins PC7 to PC0 PORTC is an 8 bit read only register that shows the pin states It cannot be written to Writing of output data for the port C pins PC7 to PC0 must always be performed on PCDR If a port C read is performed while PCDDR bits are set to 1 the PCDR values are read If a port C read is performed while ...

Page 402: ...et and in hardware standby mode It retains its prior state by a manual reset or in software standby mode Port C Open Drain Control Register PCODR 7 PC7ODR 0 R W Bit Initial value R W 6 PC6ODR 0 R W 5 PC5ODR 0 R W 4 PC4ODR 0 R W 3 PC3ODR 0 R W 2 PC2ODR 0 R W 1 PC1ODR 0 R W 0 PC0ODR 0 R W PCDDR is an 8 bit Read Write register and controls PMOS On Off of each pin PC7 to PC0 of port C If PCODR is set ...

Page 403: ...nction as address outputs or input ports and I O can be specified in bit units When each bit in PCDDR is set to 1 the corresponding pin functions as an address output and when the bit cleared to 0 the pin functions as a PWM output and an input port Figure 10 14 shows the port C pin functions A7 A6 A5 A4 A3 A2 A1 A0 output output output output output output output output PCDDR 1 PC7 PC6 PC5 PC4 PC3...

Page 404: ...corresponding pin functions as an output port and when the bit is cleared to 0 the pin functions as an input port Figure 10 15 shows the port C pin functions PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 input output PWM1 output input output PWM0 output input output input output input output input output input output input output Port C Figure 10 15 Port C Pin Functions Mode 7 ...

Page 405: ... to ON The MOS input pull up function is in the off state after a power on reset and in hardware standby mode The prior state is retained by a manual reset or in software standby mode Table 10 15 summarizes the MOS input pull up states Table 10 15 MOS Input Pull Up States Port C Pin States Power On Reset Hardware Standby Mode Manual Reset Software Standby Mode In Other Operations Address output or...

Page 406: ...ull up function that can be controlled by software Figure 10 16 shows the port D pin configuration PD7 D15 PD6 D14 PD5 D13 PD4 D12 PD3 D11 PD2 D10 PD1 D9 PD0 D8 Port D D15 D14 D13 D12 D11 D10 D9 D8 I O I O I O I O I O I O I O I O Port D pins Pin functions in modes 4 to 6 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 I O I O I O I O I O I O I O I O Pin functions in mode 7 Figure 10 16 Port D Pin Functions ...

Page 407: ...R PD3DDR PD2DDR PD1DDR PD0DDR Initial value 0 0 0 0 0 0 0 0 R W W W W W W W W W PDDDR is an 8 bit write only register the individual bits of which specify input or output for the pins of port D PDDDR cannot be read if it is an undefined value will be read PDDDR is initialized to H 00 by a power on reset and in hardware standby mode It retains its prior state by a manual reset or in software standb...

Page 408: ...D6 PD5 PD4 PD3 PD2 PD1 PD0 Initial value R W R R R R R R R R Note Determined by state of pins PD7 to PD0 PORTD is an 8 bit read only register that shows the pin states It cannot be written to Writing of output data for the port D pins PD7 to PD0 must always be performed on PDDR If a port D read is performed while PDDDR bits are set to 1 the PDDR values are read If a port D read is performed while ...

Page 409: ...DPCR is initialized to H 00 by a power on reset and in hardware standby mode It retains its prior state by a manual reset or in software standby mode 10 10 3 Pin Functions Modes 4 to 6 In modes 4 to 6 port D pins are automatically designated as data I O pins Port D pin functions in modes 4 to 6 are shown in figure 10 17 D15 D14 D13 D12 D11 D10 D9 D8 Port D I O I O I O I O I O I O I O I O Figure 10...

Page 410: ... is cleared to 0 in mode 7 setting the corresponding PDPCR bit to 1 turns on the MOS input pull up for that pin The MOS input pull up function is in the off state after a power on reset and in hardware standby mode The prior state is retained by a manual reset or in software standby mode Table 10 17 summarizes the MOS input pull up states Table 10 17 MOS Input Pull Up States Port D Modes Power On ...

Page 411: ...l up function that can be controlled by software Figure 10 19 shows the port E pin configuration PE7 D7 PE6 D6 PE5 D5 PE4 D4 PE3 D3 PE2 D2 PE1 D1 PE0 D0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 I O I O I O I O I O I O I O I O Port E pins Pin functions in modes 4 to 6 Pin functions in mode 7 D7 D6 D5 D4 D3 D2 D1 D0 I O I O I O I O I O I O I O I O PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 I O I O I O I O I O I O I O I...

Page 412: ...ecify input or output for the pins of port E PEDDR cannot be read if it is an undefined value will be read PEDDR is initialized to H 00 by a power on reset and in hardware standby mode It retains its prior state by a manual reset or in software standby mode Modes 4 to 6 When 8 bit bus mode has been selected port E pins function as I O ports Setting a PEDDR bit to 1 makes the corresponding port E p...

Page 413: ...E6 PE5 PE4 PE3 PE2 PE1 PE0 Initial value R W R R R R R R R R Note Determined by state of pins PE7 to PE0 PORTE is an 8 bit read only register that shows the pin states It cannot be written to Writing of output data for the port E pins PE7 to PE0 must always be performed on PEDR If a port E read is performed while PEDDR bits are set to 1 the PEDR values are read If a port E read is performed while ...

Page 414: ...n hardware standby mode It retains its prior state by a manual reset or in software standby mode 10 11 3 Pin Functions Modes 4 to 6 In modes 4 to 6 when 8 bit access is designated and 8 bit bus mode is selected port E pins are automatically designated as I O ports Setting a PEDDR bit to 1 makes the corresponding port E pin an output port while clearing the bit to 0 makes the pin an input port When...

Page 415: ...bit bus mode is selected or in mode 7 and can be specified as on or off on an individual bit basis When a PEDDR bit is cleared to 0 in mode 4 to 6 when 8 bit bus mode is selected or in mode 7 setting the corresponding PEPCR bit to 1 turns on the MOS input pull up for that pin The MOS input pull up function is in the off state after a power on reset and in hardware standby mode The prior state is r...

Page 416: ...ation PF7 ø PF6 AS LCAS PF5 RD PF4 HWR PF3 LWR ADTRG IRQ3 PF2 WAIT BREQO PF1 BACK BUZZ PF0 BREQ IRQ2 Port F Port F pins PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 input ø output I O I O I O I O ADTRG input IRQ3 input I O I O BUZZ output I O IRQ2 input Pin functions in mode 7 PF7 input ø output AS output LCAS output RD output HWR output PF3 I O LWR output ADTRG input IRQ3 input PF2 I O LCAS output WAIT input ...

Page 417: ...bits of which specify input or output for the pins of port F PFDDR cannot be read if it is an undefined value will be read PFDDR is initialized by a power on reset and in hardware standby mode to H 80 in modes 4 to 6 and to H 00 in mode 7 It retains its prior state by a manual reset or in software standby mode The OPE bit in SBYCR is used to select whether the bus control output pins retain their ...

Page 418: ... for the port F pins PF7 to PF0 PFDR is initialized to H 00 by a power on reset and in hardware standby mode It retains its prior state by a manual reset or in software standby mode Port F Register PORTF Bit 7 6 5 4 3 2 1 0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Initial value R W R R R R R R R R Note Determined by state of pins PF7 to PF0 PORTF is an 8 bit read only register that shows the pin states It ...

Page 419: ... function is switched as shown below according to the combination of the operating mode and bits RMTS2 to RMTS0 LCASS BREQOE WAITE ABW5 to ABW2 and PF2DDR Operating Mode Modes 4 to 6 Mode 7 LCASS 0 1 PF6DDR 0 1 Pin function AS output pin LCAS output pin PF6 input pin PF6 output pin Note Restricted to RMTS2 to TMTS0 B 001 to B 011 DRAM space 16 bit access in modes 4 to 6 only PF5 RD The pin functio...

Page 420: ...ction is switched as shown below according to the combination of the operating mode and bits RMTS2 to RMTS0 LCASS BREQOE WAITE ABW5 to ABW2 and PF2DDR Operating Mode Modes 4 to 6 Mode 7 LCASS 0 1 BREQOE 0 1 WAITE 0 1 PF2DDR 0 1 0 1 Pin function LCAS output pin PF2 input pin PF2 output pin WAIT input pin BREQO output pin PF2 input pin PF2 output pin Note Restricted to RMTS2 to TMTS0 B 001 to B 011 ...

Page 421: ...it I O port and also used as external interrupt input pins IRQ6 IRQ7 and bus control signal output pins CS0 to CS3 CAS OE Figure 10 23 shows the configuration of port G pins PG4 PG3 PG2 PG1 PG0 PG4 PG3 PG2 PG1 PG0 input input input input input output CAS output IRQ6 input CS0 CS1 CS2 CS3 OE IRQ7 CAS IRQ6 Port G pin Pin Functions in Modes 4 to 6 Port G CS0 output CS1 output CS2 output CS3 output OE...

Page 422: ...ifies I O of each pin of port G in bit units Read processing is invalid Bits 7 to 5 are reserved bits When the contents are read undefined values are read In modes 4 and 5 the PG4DDR bits are initialized to H 10 bit 4 to 0 in power on reset or hardware standby mode in modes 6 and 7 the bits are initialized to H 00 bit 4 to 0 In manual reset or software standby mode PGDDR retains the last status Us...

Page 423: ...by mode PGDR retains the last state 3 Port G Register PORTG 7 Undefined Bit Initial value R W 6 Undefined 5 Undefined 4 PG4 R 3 PG3 R 2 PG2 R 1 PG1 R 0 PG0 R Note Determined by the state of PG4 to PG0 PORTG is an 8 bit read only register and reflects the pin state Write processing is invalid Write processing of output data of port G pins PG4 to PG0 must be performed for PGDR Bits 7 to 5 are reserv...

Page 424: ... operating mode and bit PG4DDR Operating Mode Modes 4 to 6 Mode 7 PG4DDR 0 1 0 1 Pin function PG4 input pin CS0 output pin PG4 input pin PG4 output pin PG3 CS1 The pin function is switched as shown below according to the operating mode and bit PG3DDR Operating Mode Modes 4 to 6 Mode 7 PG3DDR 0 1 0 1 Pin function PG3 input pin CS1 output pin PG3 input pin PG3 output pin PG2 CS2 The pin function is ...

Page 425: ...1 0 1 OES 0 1 Pin function PG1 input pin CS3 output pin OE output pin PG1 input pin PG1 output pin IRQ7 input PG0 CAS IRQ6 The pin function is switched as shown below according to the operating mode and bits RMTS2 to RMTS0 in BCRH Operating Mode Modes 4 to 6 Mode 7 RMTS2 to RMTS0 B 000 B 001 to B 011 PG0DDR 0 1 0 1 Pin function PG0 input pin PG0 output pin CAS output pin PG0 input pin PG0 output p...

Page 426: ...e detection Counter clear operation Counter clearing possible by compare match or input capture Synchronous operation Multiple timer counters TCNT can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input output possible by counter synchronous operation PWM mode Any PWM output duty can be set Maximum of 15 phase PWM output possib...

Page 427: ...ta transfer and 1 byte data transfer possible by data transfer controller DTC or DMA controller DMAC Programmable pulse generator PPG output trigger can be generated Channel 0 to 3 compare match input capture signals can be used as PPG output trigger A D converter conversion start trigger can be generated Channel 0 to 5 compare match A input capture A signals can be used as A D converter conversio...

Page 428: ... TGR2B TGR3A TGR3B TGR4A TGR4B TGR5A TGR5B General registers buffer registers TGR0C TGR0D TGR3C TGR3D I O pins TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare ma...

Page 429: ...e match or input capture PPG trigger TGR0A TGR0B compare match or input capture TGR1A TGR1B compare match or input capture TGR2A TGR2B compare match or input capture TGR3A TGR3B compare match or input capture Interrupt sources 5 sources Compare match or input capture 0A Compare match or input capture 0B Compare match or input capture 0C Compare match or input capture 0D Overflow 4 sources Compare ...

Page 430: ... TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 Interrupt request signals Channel 3 Channel 4 Channel 5 Interrupt request signals Channel 0 Channel 1 Channel 2 Internal data bus A D converter convertion start signal PPG output trigger signal TIORL Module data bus TGI3A TGI3B TGI3C TGI3D TCI3V TGI4A TGI4B TCI4V TCI4U TGI5A TGI5B TCI5V TCI5U TGI0A TGI0B TGI0C TGI0D TCI0V TGI1A TGI1B TCI1V TCI1U TGI2A TGI...

Page 431: ...ut output compare output PWM output pin Input capture out compare match B0 TIOCB0 I O TGR0B input capture input output compare output PWM output pin Input capture out compare match C0 TIOCC0 I O TGR0C input capture input output compare output PWM output pin Input capture out compare match D0 TIOCD0 I O TGR0D input capture input output compare output PWM output pin 1 Input capture out compare match...

Page 432: ...utput pin Input capture out compare match D3 TIOCD3 I O TGR3D input capture input output compare output PWM output pin 4 Input capture out compare match A4 TIOCA4 I O TGR4A input capture input output compare output PWM output pin Input capture out compare match B4 TIOCB4 I O TGR4B input capture input output compare output PWM output pin 5 Input capture out compare match A5 TIOCA5 I O TGR5A input c...

Page 433: ...FFFF H FF1C Timer general register 0D TGR0D R W H FFFF H FF1E 1 Timer control register 1 TCR1 R W H 00 H FF20 Timer mode register 1 TMDR1 R W H C0 H FF21 Timer I O control register 1 TIOR1 R W H 00 H FF22 Timer interrupt enable register 1 TIER1 R W H 40 H FF24 Timer status register 1 TSR1 R W 2 H C0 H FF25 Timer counter 1 TCNT1 R W H 0000 H FF26 Timer general register 1A TGR1A R W H FFFF H FF28 Ti...

Page 434: ... I O control register 4 TIOR4 R W H 00 H FE92 Timer interrupt enable register 4 TIER4 R W H 40 H FE94 Timer status register 4 TSR4 R W 2 H C0 H FE95 Timer counter 4 TCNT4 R W H 0000 H FE96 Timer general register 4A TGR4A R W H FFFF H FE98 Timer general register 4B TGR4B R W H FFFF H FE9A 5 Timer control register 5 TCR5 R W H 00 H FEA0 Timer mode register 5 TMDR5 R W H C0 H FEA1 Timer I O control r...

Page 435: ...nel 2 TCR2 Channel 4 TCR4 Channel 5 TCR5 Bit 7 6 5 4 3 2 1 0 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W The TCR registers are 8 bit registers that control the TCNT channels The TPU has six TCR registers one for each of channels 0 to 5 The TCR registers are initialized to H 00 by a reset and in hardware standby mode TCR register settings ...

Page 436: ...leared by counter clearing for another channel performing synchronous clearing synchronous operation 1 Bit 7 Bit 6 Bit 5 Channel Reserved 3 CCLR1 CCLR0 Description 1 2 4 5 0 0 0 TCNT clearing disabled Initial value 1 TCNT cleared by TGRA compare match input capture 1 0 TCNT cleared by TGRB compare match input capture 1 TCNT cleared by counter clearing for another channel performing synchronous cle...

Page 437: ...t both edges Note Internal clock edge selection is valid when the input clock is ø 4 or slower This setting is ignored if the input clock is ø 1 or when overflow underflow of another channel is selected Bits 2 1 and 0 Time Prescaler 2 1 and 0 TPSC2 to TPSC0 These bits select the TCNT counter clock The clock source can be selected independently for each channel Table 11 4 shows the clock sources th...

Page 438: ...ernal clock counts on ø 16 1 Internal clock counts on ø 64 1 0 0 External clock counts on TCLKA pin input 1 External clock counts on TCLKB pin input 1 0 Internal clock counts on ø 256 1 Counts on TCNT2 overflow underflow Note This setting is ignored when channel 1 is in phase counting mode Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description 2 0 0 0 Internal clock counts on ø 1 Initial value 1 ...

Page 439: ...unts on ø 16 1 Internal clock counts on ø 64 1 0 0 External clock counts on TCLKA pin input 1 External clock counts on TCLKC pin input 1 0 Internal clock counts on ø 1024 1 Counts on TCNT5 overflow underflow Note This setting is ignored when channel 4 is in phase counting mode Bit 2 Bit 1 Bit 0 Channel TPSC2 TPSC1 TPSC0 Description 5 0 0 0 Internal clock counts on ø 1 Initial value 1 Internal cloc...

Page 440: ...The TMDR registers are initialized to H C0 by a reset and in hardware standby mode TMDR register settings should be made only when TCNT operation is stopped Bits 7 and 6 Reserved These bits are always read as 1 and cannot be modified Bit 5 Buffer Operation B BFB Specifies whether TGRB is to operate in the normal way or TGRB and TGRD are to be used together for buffer operation When TGRD is used as...

Page 441: ...rmally Initial value 1 TGRA and TGRC used together for buffer operation Bits 3 to 0 Modes 3 to 0 MD3 to MD0 These bits are used to set the timer operating mode Bit 3 Bit 2 Bit 1 Bit 0 MD3 1 MD2 2 MD1 MD0 Description 0 0 0 0 Normal operation Initial value 1 Reserved 1 0 PWM mode 1 1 PWM mode 2 1 0 0 Phase counting mode 1 1 Phase counting mode 2 1 0 Phase counting mode 3 1 Phase counting mode 4 1 Do...

Page 442: ...C or TGRD is designated for buffer operation this setting is invalid and the register operates as a buffer register The TIOR registers are 8 bit registers that control the TGR registers The TPU has eight TIOR registers two each for channels 0 and 3 and one each for channels 1 2 4 and 5 The TIOR registers are initialized to H 00 by a reset and in hardware standby mode Care is required since TIOR is...

Page 443: ...ch Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 1 0 1 TGR0B is input capture register Capture input source is TIOCB0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 Capture input source is channel 1 count clock Input captur...

Page 444: ...are match 1 0 0 1 0 1 TGR0D is input capture register 2 Capture input source is TIOCD0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 Capture input source is channel 1 count clock Input capture at TCNT1 count up count down 1 Don t care Notes 1 When bits TPSC2 to TPSC0 in TCR1 are set to B 000 and ø 1 is used as the TCNT1 count clock this setting is inv...

Page 445: ...ge Input capture at both edges 1 Capture input source is TGR0C compare match input capture Input capture at generation of TGR0C compare match input capture Don t care Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description 2 0 0 0 0 TGR2B is Output disabled Initial value 1 1 0 1 output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle ou...

Page 446: ...at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 1 0 1 TGR3B is input capture register Capture input source is TIOCB3 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 Capture input source is channel 4 count clock Input capture at TCNT4 count up count down 1 Don t care Note 1 When bits TPSC2 to TPSC0 in TCR4 are...

Page 447: ...are match 1 0 0 1 0 1 TGR3D is input capture register 2 Capture input source is TIOCD3 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 Capture input source is channel 4 count clock Input capture at TCNT4 count up count down 1 Don t care Notes 1 When bits TPSC2 to TPSC0 in TCR4 are set to B 000 and ø 1 is used as the TCNT4 count clock this setting is inv...

Page 448: ...ge Input capture at both edges 1 Capture input source is TGR3C compare match input capture Input capture at generation of TGR3C compare match input capture Don t care Bit 7 Bit 6 Bit 5 Bit 4 Channel IOB3 IOB2 IOB1 IOB0 Description 5 0 0 0 0 TGR5B is Output disabled Initial value 1 1 0 1 output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle ou...

Page 449: ...nitial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 1 0 1 TGR0A is input capture register Capture input source is TIOCA0 pin Input capture at rising edge Input capture at falling edge Input capture...

Page 450: ... at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 1 0 1 TGR0C is input capture register 1 Capture input source is TIOCC0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 Capture input source is channel 1 count clock Input capture at TCNT1 count up count down Don t care Note 1 When the BFA bit in TMDR0 is set to...

Page 451: ...put capture at both edges 1 Capture input source is TGR0A compare match input capture Input capture at generation of channel 0 TGR0A compare match input capture Don t care Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description 2 0 0 0 0 TGR2A is Output disabled Initial value 1 1 0 1 output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Togg...

Page 452: ...le output at compare match 1 0 0 Output disabled 1 Initial output is 1 0 output at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 1 0 1 TGR3A is input capture register Capture input source is TIOCA3 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 Capture input source is channel 4 count clock Input capture at TC...

Page 453: ... at compare match 1 0 output 1 output at compare match 1 Toggle output at compare match 1 0 0 1 0 1 TGR3C is input capture register 1 Capture input source is TIOCC3 pin Input capture at rising edge Input capture at falling edge Input capture at both edges 1 Capture input source is channel 4 count clock Input capture at TCNT4 count up count down Don t care Note 1 When the BFA bit in TMDR3 is set to...

Page 454: ...ge Input capture at both edges 1 Capture input source is TGR3A compare match input capture Input capture at generation of TGR3A compare match input capture Don t care Bit 3 Bit 2 Bit 1 Bit 0 Channel IOA3 IOA2 IOA1 IOA0 Description 5 0 0 0 0 TGR5A is Output disabled Initial value 1 1 0 1 output compare register Initial output is 0 output 0 output at compare match 1 output at compare match Toggle ou...

Page 455: ...TIER1 Channel 2 TIER2 Channel 4 TIER4 Channel 5 TIER5 Bit 7 6 5 4 3 2 1 0 TTGE TCIEU TCIEV TGIEB TGIEA Initial value 0 1 0 0 0 0 0 0 R W R W R W R W R W R W The TIER registers are 8 bit registers that control enabling or disabling of interrupt requests for each channel The TPU has six TIER registers one for each channel The TIER registers are initialized to H 40 by a reset and in hardware standby ...

Page 456: ...0 and cannot be modified Bit 5 TCIEU Description 0 Interrupt requests TCIU by TCFU disabled Initial value 1 Interrupt requests TCIU by TCFU enabled Bit 4 Overflow Interrupt Enable TCIEV Enables or disables interrupt requests TCIV by the TCFV flag when the TCFV flag in TSR is set to 1 Bit 4 TCIEV Description 0 Interrupt requests TCIV by TCFV disabled Initial value 1 Interrupt requests TCIV by TCFV ...

Page 457: ... TGIC by TGFC bit enabled Bit 1 TGR Interrupt Enable B TGIEB Enables or disables interrupt requests TGIB by the TGFB bit when the TGFB bit in TSR is set to 1 Bit 1 TGIEB Description 0 Interrupt requests TGIB by TGFB bit disabled Initial value 1 Interrupt requests TGIB by TGFB bit enabled Bit 0 TGR Interrupt Enable A TGIEA Enables or disables interrupt requests TGIA by the TGFA bit when the TGFA bi...

Page 458: ...Channel 1 TSR1 Channel 2 TSR2 Channel 4 TSR4 Channel 5 TSR5 Bit 7 6 5 4 3 2 1 0 TCFD TCFU TCFV TGFB TGFA Initial value 1 1 0 0 0 0 0 0 R W R R W R W R W R W Note Only 0 can be written for flag clearing The TSR registers are 8 bit registers that indicate the status of each channel The TPU has six TSR registers one for each channel The TSR registers are initialized to H C0 by a reset and in hardware...

Page 459: ...low has occurred when channels 1 2 4 and 5 are set to phase counting mode In channels 0 and 3 bit 5 is reserved It is always read as 0 and cannot be modified Bit 5 TCFU Description 0 Clearing condition Initial value When 0 is written to TCFU after reading TCFU 1 1 Setting condition When the TCNT value underflows changes from H 0000 to H FFFF Bit 4 Overflow Flag TCFV Status flag that indicates that...

Page 460: ...lue is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Bit 2 Input Capture Output Compare Flag C TGFC Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3 In channels 1 2 4 and 5 bit 2 is reserved It is always read as 0 and cannot be modified Bit 2 TGFC Description 0 Clearing conditions Initial value Wh...

Page 461: ...ture signal while TGRB is functioning as input capture register Bit 0 Input Capture Output Compare Flag A TGFA Status flag that indicates the occurrence of TGRA input capture or compare match Bit 0 TGFA Description 0 Clearing conditions Initial value When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC i...

Page 462: ...R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Note These counters can be used as up down counters only in phase counting mode or when counting overflow underflow on another channel In other cases they function as up counters The TCNT registers are 16 bit counters The TPU has six TCNT counters one for each channel The TCNT counters are initialized to H 0000 by a reset and in hardware ...

Page 463: ...are and input capture registers The TPU has 16 TGR registers four each for channels 0 and 3 and two each for channels 1 2 4 and 5 TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers The TGR registers are initialized to H FFFF by a reset and in hardware standby mode The TGR registers cannot be accessed in 8 bit units they must always be accessed as a 16 bit u...

Page 464: ... first stop the TCNT counter Bits 7 and 6 Reserved Should always be written with 0 Bits 5 to 0 Counter Start 5 to 0 CST5 to CST0 These bits select operation or stoppage for TCNT Bit n CSTn Description 0 TCNTn count operation is stopped Initial value 1 TCNTn performs count operation n 5 to 0 Note If 0 is written to the CST bit during operation with the TIOC pin designated for output the counter sto...

Page 465: ...YNC5 to SYNC0 These bits select whether operation is independent of or synchronized with other channels When synchronous operation is selected synchronous presetting of multiple channels 1 and synchronous clearing through counter clearing on another channel 2 are possible Bit n SYNCn Description 0 TCNTn operates independently TCNT presetting clearing is unrelated to other channels Initial value 1 ...

Page 466: ... set to 1 TPU operation stops at the end of the bus cycle and a transition is made to module stop mode Registers cannot be read or written to in module stop mode For details see section 24 5 Module Stop Mode MSTPCRA is initialized to H 3F by a power on reset and in hardware standby mode It is not initialized by a manual reset and in software standby mode Bit 5 Module Stop MSTPA5 Specifies the TPU ...

Page 467: ...it access must always be used An example of 16 bit register access operation is shown in figure 11 2 Bus interface H Internal data bus L Bus master Module data bus TCNTH TCNTL Figure 11 2 16 Bit Register Access Operation Bus Master TCNT 16 Bits 11 3 2 8 Bit Registers Registers other than TCNT and TGR are 8 bit As the data bus to the CPU is 16 bits wide these registers can be read and written to in...

Page 468: ...gure 11 3 8 Bit Register Access Operation Bus Master TCR Upper 8 Bits Bus interface H Internal data bus L Module data bus TMDR Bus master Figure 11 4 8 Bit Register Access Operation Bus Master TMDR Lower 8 Bits Bus interface H Internal data bus L Module data bus TCR TMDR Bus master Figure 11 5 8 Bit Register Access Operation Bus Master TCR and TMDR 16 Bits ...

Page 469: ...mpare register When a compare match occurs the value in the buffer register for the relevant channel is transferred to TGR When TGR is an input capture register When input capture occurs the value in TCNT is transfer to TGR and the value previously held in TGR is transferred to the buffer register Cascaded Operation The channel 1 counter TCNT1 channel 2 counter TCNT2 channel 4 counter TCNT4 and ch...

Page 470: ...unt operation Periodic counter 1 2 4 3 5 Free running counter Start count operation Free running counter 5 1 2 3 4 5 Select output compare register Select the counter clock with bits TPSC2 to TPSC0 in TCR At the same time select the input clock edge with bits CKEG1 and CKEG0 in TCR For periodic counter operation select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR ...

Page 471: ...FFFF H 0000 CST bit TCFV Time Figure 11 7 Free Running Counter Operation When compare match is selected as the TCNT clearing source the TCNT counter for the relevant channel performs periodic count operation The TGR register for setting the period is designated as an output compare register and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR After the settings ...

Page 472: ... match Figure 11 9 shows an example of the setting procedure for waveform output by compare match Select waveform output mode Output selection Set output timing Start count operation Waveform output 1 2 3 1 Select initial value 0 output or 1 output and compare match output value 0 output 1 output or toggle output by means of TIOR The set initial value is output at the TIOC pin until the first comp...

Page 473: ...0 TIOCA TIOCB Time TGRA TGRB No change No change No change No change 1 output 0 output Figure 11 10 Example of 0 Output 1 Output Operation Figure 11 11 shows an example of toggle output In this example TCNT has been designated as a periodic counter with counter clearing performed by compare match B and settings have been made so that output is toggled by both compare match A and compare match B TC...

Page 474: ...1 should not be selected as the counter input clock used for input capture input Input capture will not be generated if ø 1 is selected Example of input capture operation setting procedure Figure 11 12 shows an example of the input capture operation setting procedure Select input capture input Input selection Start count Input capture operation 1 2 1 Designate TGR as an input capture register by m...

Page 475: ...IOCA pin input capture input edge falling edge has been selected as the TIOCB pin input capture input edge and counter clearing by TGRB input capture has been designated for TCNT TCNT value H 0180 H 0000 TIOCA TGRA Time H 0010 H 0005 Counter cleared by TIOCB input falling edge H 0160 H 0005 H 0160 H 0010 TGRB H 0180 TIOCB Figure 11 13 Example of Input Capture Operation ...

Page 476: ...ing Synchronous presetting 1 2 Synchronous clearing Select counter clearing source Counter clearing 3 Start count 5 Set synchronous counter clearing Synchronous clearing 4 Start count 5 Clearing sourcegeneration channel No Yes 1 2 3 4 5 Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation When the TCNT counter of any of the channels designated for...

Page 477: ...and 2 counter clearing source Three phase PWM waveforms are output from pins TIOC0A TIOC1A and TIOC2A At this time synchronous presetting and synchronous clearing by TGR0B compare match is performed for channel 0 to 2 TCNT counters and the data set in TGR0B is used as the PWM cycle For details of PWM modes see section 11 4 6 PWM Modes TCNT0 to TCNT2 values H 0000 TIOC0A TIOC1A Time TGR0B Synchrono...

Page 478: ... buffer operation Table 11 5 Register Combinations in Buffer Operation Channel Timer General Register Buffer Register 0 TGR0A TGR0C TGR0B TGR0D 3 TGR3A TGR3C TGR3B TGR3D When TGR is an output compare register When a compare match occurs the value in the buffer register for the corresponding channel is transferred to the timer general register This operation is illustrated in figure 11 16 Buffer re...

Page 479: ...e 11 17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure Figure 11 18 shows an example of the buffer operation setting procedure Select TGR function Buffer operation Set buffer operation Start count Buffer operation 1 2 3 1 Designate TGR as an input capture register or output compare register by means of TIOR 2 Designate TGR for buffer operation with bits BFA and BFB in...

Page 480: ... at compare match A and 0 output at compare match B As buffer operation has been set when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA This operation is repeated each time compare match A occurs For details of PWM modes see section 11 4 6 PWM Modes TCNT value TGR0B H 0000 TGR0C Time TGR0A H 0200 H 0520 ...

Page 481: ...ture has been set for TCNT and both rising and falling edges have been selected as the TIOCA pin input capture input edge As buffer operation has been set when the TCNT value is stored in TGRA upon occurrence of input capture A the value previously stored in TGRA is simultaneously transferred to TGRC TCNT value H 09FB H 0000 TGRC Time H 0532 TIOCA TGRA H 0F07 H 0532 H 0F07 H 0532 H 0F07 H 09FB Fig...

Page 482: ...the counter clock setting is invalid and the counter operates independently in phase counting mode Table 11 6 Cascaded Combinations Combination Upper 16 Bits Lower 16 Bits Channels 1 and 2 TCNT1 TCNT2 Channels 4 and 5 TCNT4 TCNT5 Example of Cascaded Operation Setting Procedure Figure 11 21 shows an example of the setting procedure for cascaded operation Set cascading Cascaded operation Start count...

Page 483: ...ferred to TGR1A and the lower 16 bits to TGR2A TCNT2 clock TCNT2 H FFFF H 0000 H 0001 TIOCA1 TIOCA2 TGR1A H 03A2 TGR2A H 0000 TCNT1 clock TCNT1 H 03A1 H 03A2 Figure 11 22 Example of Cascaded Operation 1 Figure 11 23 illustrates the operation when counting upon TCNT2 overflow underflow has been set for TCNT1 and phase counting mode has been designated for channel 2 TCNT1 is incremented by TCNT2 ove...

Page 484: ... IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D The initial output value is the value set in TGRA or TGRC If the set values of paired TGRs are identical the output value does not change when a compare match occurs In PWM mode 1 a maximum 8 phase PWM output is possible PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers...

Page 485: ...B0 TGR0C TIOCC0 TIOCC0 TGR0D TIOCD0 1 TGR1A TIOCA1 TIOCA1 TGR1B TIOCB1 2 TGR2A TIOCA2 TIOCA2 TGR2B TIOCB2 3 TGR3A TIOCA3 TIOCA3 TGR3B TIOCB3 TGR3C TIOCC3 TIOCC3 TGR3D TIOCD3 4 TGR4A TIOCA4 TIOCA4 TGR4B TIOCB4 5 TGR5A TIOCA5 TIOCA5 TGR5B TIOCB5 Note In PWM mode 2 PWM output is not possible for the TGR register in which the period is set ...

Page 486: ...designate the TGR as an output compare register and select the initial value and output value 4 Set the cycle in the TGR selected in 2 and set the duty in the other the TGR 5 Select the PWM mode with bits MD3 to MD0 in TMDR 6 Set the CST bit in TSTR to 1 to start the count operation Figure 11 24 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation Figure 11 25 shows an example of P...

Page 487: ...ch is set as the TCNT clearing source and 0 is set for the initial output value and 1 for the output value of the other TGR registers TGR0A to TGR0D TGR1A to output a 5 phase PWM waveform In this case the value set in TGR1B is used as the cycle and the values set in the other TGRs as the duty TCNT value TGR1B H 0000 TIOCA0 Counter cleared by TGR1B compare match TGR1A TGR0D TGR0C TGR0B TGR0A TIOCB0...

Page 488: ...IOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRA H 0000 TIOCA Time TGRB 100 duty TGRB rewritten TGRB rewritten TGRB rewritten Output does not change when cycle register and duty register compare matches occur simultaneously 0 duty Figure 11 27 Example of PWM Mode Op...

Page 489: ...w occurs while TCNT is counting down the TCFU flag is set The TCFD bit in TSR is the count direction flag Reading the TCFD flag provides an indication of whether TCNT is counting up or down Table 11 8 shows the correspondence between external clock pins and channels Table 11 8 Phase Counting Mode Clock Input Pins External Clock Pins Channels A Phase B Phase When channel 1 or 5 is set to phase coun...

Page 490: ...zes the TCNT up down count conditions TCNT value Time Down count Up count TCLKA channels 1 and 5 TCLKC channels 2 and 4 TCLKB channels 1 and 5 TCLKD channels 2 and 4 Figure 11 29 Example of Phase Counting Mode 1 Operation Table 11 9 Up Down Count Conditions in Phase Counting Mode 1 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Up c...

Page 491: ... and 5 TCLKD Channels 2 and 4 Figure 11 30 Example of Phase Counting Mode 2 Operation Table 11 10 Up Down Count Conditions in Phase Counting Mode 2 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Don t care Low level Don t care High level Don t care L...

Page 492: ...D channels 2 and 4 Down count Figure 11 31 Example of Phase Counting Mode 3 Operation Table 11 11 Up Down Count Conditions in Phase Counting Mode 3 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Don t care Low level Don t care Low level Don t care High level Up count High level Down count Low level Don t care High level Don t care L...

Page 493: ...LKD channels 2 and 4 Up count Down count TCNT value Figure 11 32 Example of Phase Counting Mode 4 Operation Table 11 12 Up Down Count Conditions in Phase Counting Mode 4 TCLKA Channels 1 and 5 TCLKC Channels 2 and 4 TCLKB Channels 1 and 5 TCLKD Channels 2 and 4 Operation High level Up count Low level Low level Don t care High level High level Down count Low level High level Don t care Low level Le...

Page 494: ...nd TGR0C are used for the compare match function and are set with the speed control period and position control period TGR0B is used for input capture with TGR0B and TGR0D operating in buffer mode The channel 1 counter input clock is designated as the TGR0B input capture source and detection of the pulse width of 2 phase encoder 4 multiplication pulses is performed TGR1A and TGR1B for channel 1 ar...

Page 495: ...od capture TGR0A speed control period TGR1B position period capture TGR0C position control period TGR0B pulse width capture TGR0D buffer operation Channel 0 TCLKA TCLKB Edge detection circuit Figure 11 33 Phase Counting Mode Application Example ...

Page 496: ... enabled or disabled individually When an interrupt request is generated the corresponding status flag in TSR is set to 1 If the corresponding enable disable bit in TIER is set to 1 at this time an interrupt is requested The interrupt request is cleared by clearing the status flag to 0 Relative channel priorities can be changed by the interrupt controller but the priority order within a channel is...

Page 497: ...2 overflow Not possible Not possible TCI2U TCNT2 underflow Not possible Not possible 3 TGI3A TGR3A input capture compare match Possible Possible TGI3B TGR3B input capture compare match Not possible Possible TGI3C TGR3C input capture compare match Not possible Possible TGI3D TGR3D input capture compare match Not possible Possible TCI3V TCNT3 overflow Not possible Not possible 4 TGI4A TGR4A input ca...

Page 498: ...tion DTC Activation The DTC can be activated by the TGR input capture compare match interrupt for a channel For details see section 9 Data Transfer Controller A total of 16 TPU input capture compare match interrupts can be used as DTC activation sources four each for channels 0 and 3 and two each for channels 1 2 4 and 5 DMAC Activation It is possible to activate the DMAC by the TGRA input capture...

Page 499: ...figure 11 35 shows TCNT count timing in external clock operation TCNT TCNT input clock Internal clock ø N 1 N N 1 N 2 Falling edge Rising edge Figure 11 34 Count Timing in Internal Clock Operation TCNT TCNT input clock External clock ø N 1 N N 1 N 2 Rising edge Falling edge Falling edge Figure 11 35 Count Timing in External Clock Operation ...

Page 500: ...are output pin After a match between TCNT and TGR the compare match signal is not generated until the TCNT input clock is generated Figure 11 36 shows output compare output timing TGR TCNT TCNT input clock ø N N N 1 Compare match signal TIOC pin Figure 11 36 Output Compare Output Timing Input Capture Signal Timing Figure 11 37 shows input capture signal timing TCNT Input capture input ø N N 1 N 2 ...

Page 501: ...rence is specified and figure 11 39 shows the timing when counter clearing by input capture occurrence is specified TCNT Counter clear signal Compare match signal ø TGR N N H 0000 Figure 11 38 Counter Clear Timing Compare Match TCNT Counter clear signal Input capture signal ø TGR N H 0000 N Figure 11 39 Counter Clear Timing Input Capture ...

Page 502: ...the timing in buffer operation TGRA TGRB Compare match signal TCNT ø TGRC TGRD n N N n n 1 Figure 11 40 Buffer Operation Timing Compare Match TGRA TGRB TCNT Input capture signal ø TGRC TGRD N n n N 1 N N N 1 Figure 11 41 Buffer Operation Timing Input Capture ...

Page 503: ...ompare Match Figure 11 42 shows the timing for setting of the TGF flag in TSR by compare match occurrence and TGI interrupt request signal timing TGR TCNT TCNT input clock ø N N N 1 Compare match signal TGF flag TGI interrupt Figure 11 42 TGI Interrupt Timing Compare Match ...

Page 504: ...Capture Figure 11 43 shows the timing for setting of the TGF flag in TSR by input capture occurrence and TGI interrupt request signal timing TGR TCNT Input capture signal ø N N TGF flag TGI interrupt Figure 11 43 TGI Interrupt Timing Input Capture ...

Page 505: ... shows the timing for setting of the TCFU flag in TSR by underflow occurrence and TCIU interrupt request signal timing Overflow signal TCNT overflow TCNT input clock ø H FFFF H 0000 TCFV flag TCIV interrupt Figure 11 44 TCIV Interrupt Setting Timing Underflow signal TCNT underflow TCNT input clock ø H 0000 H FFFF TCFU flag TCIU interrupt Figure 11 45 TCIU Interrupt Setting Timing ...

Page 506: ...the CPU and figure 11 47 shows the timing for status flag clearing by the DTC or DMAC Status flag Write signal Address ø TSR address Interrupt request signal TSR write cycle T1 T2 Figure 11 46 Timing for Status Flag Clearing by CPU Interrupt request signal Status flag Address ø Source address DTC DMAC read cycle T1 T2 Destination address T1 T2 DTC DMAC write cycle Figure 11 47 Timing for Status Fl...

Page 507: ...tes Figure 11 48 shows the input clock conditions in phase counting mode Overlap Phase differ ence Phase differ ence Overlap TCLKA TCLKC TCLKB TCLKD Pulse width Pulse width Pulse width Pulse width Notes Phase difference and overlap Pulse width 1 5 states or more 2 5 states or more Figure 11 48 Phase Difference Overlap and Pulse Width in Phase Counting Mode Caution on Period Setting When counter cl...

Page 508: ...he T2 state of a TCNT write cycle TCNT clearing takes precedence and the TCNT write is not performed Figure 11 49 shows the timing in this case Counter clear signal Write signal Address ø TCNT address TCNT TCNT write cycle T1 T2 N H 0000 Figure 11 49 Contention between TCNT Write and Clear Operations ...

Page 509: ...te of a TCNT write cycle the TCNT write takes precedence and TCNT is not incremented Figure 11 50 shows the timing in this case TCNT input clock Write signal Address ø TCNT address TCNT TCNT write cycle T1 T2 N M TCNT write data Figure 11 50 Contention between TCNT Write and Increment Operations ...

Page 510: ...ce and the compare match signal is inhibited A compare match does not occur even if the same value as before is written Figure 11 51 shows the timing in this case Compare match signal Write signal Address ø TGR address TCNT TGR write cycle T1 T2 N M TGR write data TGR N N 1 Inhibited Figure 11 51 Contention between TGR Write and Compare Match ...

Page 511: ...transferred to TGR by the buffer operation will be the data prior to the write Figure 11 52 shows the timing in this case Compare match signal Write signal Address ø Buffer register address Buffer register TGR write cycle T1 T2 N TGR N M Buffer register write data Figure 11 52 Contention between Buffer Register Write and Compare Match ...

Page 512: ...1 state of a TGR read cycle the data that is read will be the data after input capture transfer Figure 11 53 shows the timing in this case Input capture signal Read signal Address ø TGR address TGR TGR read cycle T1 T2 M Internal data bus X M Figure 11 53 Contention between TGR Read and Input Capture ...

Page 513: ...state of a TGR write cycle the input capture operation takes precedence and the write to TGR is not performed Figure 11 54 shows the timing in this case Input capture signal Write signal Address ø TCNT TGR write cycle T1 T2 M TGR M TGR address Figure 11 54 Contention between TGR Write and Input Capture ...

Page 514: ...e the buffer operation takes precedence and the write to the buffer register is not performed Figure 11 55 shows the timing in this case Input capture signal Write signal Address ø TCNT Buffer register write cycle T1 T2 N TGR N M M Buffer register Buffer register address Figure 11 55 Contention between Buffer Register Write and Input Capture ...

Page 515: ...TCFV TCFU flag in TSR is not set and TCNT clearing takes precedence Figure 11 56 shows the operation timing when a TGR compare match is specified as the clearing source and H FFFF is set in TGR Counter clear signal TCNT input clock ø TCNT TGF Disabled TCFV H FFFF H 0000 Figure 11 56 Contention between Overflow and Counter Clearing ...

Page 516: ... Contention between TCNT Write and Overflow Multiplexing of I O Pins In the H8S 2633 Series the TCLKA input pin is multiplexed with the TIOCC0 I O pin the TCLKB input pin with the TIOCD0 I O pin the TCLKC input pin with the TIOCB1 I O pin and the TCLKD input pin with the TIOCB2 I O pin When an external clock is input compare match output should not be performed from a multiplexed pin Interrupts an...

Page 517: ...nals can be selected in 4 bit groups to provide up to two different 4 bit outputs Selectable output trigger signals Output trigger signals can be selected for each group from the compare match signals of four TPU channels Non overlap mode A non overlap margin can be provided between pulse outputs Can operate together with the data transfer controller DTC and DMA controller DMAC The compare match s...

Page 518: ...xt data enable register H Next data enable register L Next data register H Next data register L Output data register H Output data register L Internal data bus PMR PCR NDERH NDERL NDRH NDRL PODRH PODRL Pulse output pins group 3 Pulse output pins group 2 Pulse output pins group 1 Pulse output pins group 0 PODRH PODRL NDRH NDRL Control logic NDERH PMR NDERL PCR Figure 12 1 Block Diagram of PPG ...

Page 519: ...Name Symbol I O Function Pulse output 8 PO8 Output Group 2 pulse output Pulse output 9 PO9 Output Pulse output 10 PO10 Output Pulse output 11 PO11 Output Pulse output 12 PO12 Output Group 3 pulse output Pulse output 13 PO13 Output Pulse output 14 PO14 Output Pulse output 15 PO15 Output ...

Page 520: ...1 data direction register P1DDR W H 00 H FE30 Module stop control register A MSTPCRA R W H 3F H FDE8 Notes 1 Lower 16 bits of the address 2 A bit that has been set for pulse output by NDER is read only 3 When the same output trigger is selected for pulse output groups 2 and 3 by the PCR setting the NDRH address is H FE2C When the output triggers are different the NDRH address is H FE2E for group 2...

Page 521: ...ue is automatically transferred to the corresponding PODR bit when the TPU compare match event specified by PCR occurs updating the output value If pulse output is disabled the bit value is not transferred from NDR to PODR and the output value does not change NDERH and NDERL are each initialized to H 00 by a reset and in hardware standby mode They are not initialized in software standby mode NDERH...

Page 522: ...0 12 2 2 Output Data Registers H and L PODRH PODRL PODRH Bit 7 6 5 4 3 2 1 0 POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W PODRL Bit 7 6 5 4 3 2 1 0 POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Note A bit that has been set for pulse output by NDER is read only PODRH and PO...

Page 523: ... the same output trigger or different output triggers Same Trigger for Pulse Output Groups If pulse output groups 2 and 3 are triggered by the same compare match event the NDRH address is H FE2C The upper 4 bits belong to group 3 and the lower 4 bits to group 2 Address H FE2E consists entirely of reserved bits that cannot be modified and are always read as 1 Address H FE2C Bit 7 6 5 4 3 2 1 0 NDR1...

Page 524: ...s H FE2E are reserved bits that cannot be modified and are always read as 1 Address H FE2C Bit 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 Initial value 0 0 0 0 1 1 1 1 R W R W R W R W R W Address H FE2E Bit 7 6 5 4 3 2 1 0 NDR11 NDR10 NDR9 NDR8 Initial value 1 1 1 1 0 0 0 0 R W R W R W R W R W If pulse output groups 0 and 1 are triggered by different compare match event the address of the upper 4 bit...

Page 525: ... 8 bit readable writable register that selects output trigger signals for PPG outputs on a group by group basis PCR is initialized to H FF by a reset and in hardware standby mode It is not initialized in software standby mode Bits 7 and 6 Group 3 Compare Match Select 1 and 0 G3CMS1 G3CMS0 These bits select the compare match that triggers pulse output group 3 pins PO15 to PO12 Bit 7 Bit 6 Descripti...

Page 526: ... Series has no output pins corresponding to pulse output group 1 Bit 3 Bit 2 Description G1CMS1 G1CMS0 Output Trigger for Pulse Output Group 1 0 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Initial value Bits 1 and 0 Group 0 Compare Match Select 1 and 0 G0CMS1 G0CMS0 These bits select the compare match that tr...

Page 527: ... is initialized to H F0 by a reset and in hardware standby mode It is not initialized in software standby mode Bit 7 Group 3 Inversion G3INV Selects direct output or inverted output for pulse output group 3 pins PO15 to PO12 Bit 7 G3INV Description 0 Inverted output for pulse output group 3 low level output at pin for a 1 in PODRH 1 Direct output for pulse output group 3 high level output at pin f...

Page 528: ...L 1 Direct output for pulse output group 0 high level output at pin for a 1 in PODRL Initial value Bit 3 Group 3 Non Overlap G3NOV Selects normal or non overlapping operation for pulse output group 3 pins PO15 to PO12 Bit 3 G3NOV Description 0 Normal operation in pulse output group 3 output values updated at compare match A in the selected TPU channel Initial value 1 Non overlapping operation in p...

Page 529: ...in pulse output group 1 independent 1 and 0 output at compare match A or B in the selected TPU channel Bit 0 Group 0 Non Overlap G0NOV Selects normal or non overlapping operation for pulse output group 0 pins PO3 to PO0 However the H8S 2633 Series has no pins corresponding to pulse output group 0 Bit 0 G0NOV Description 0 Normal operation in pulse output group 0 output values updated at compare ma...

Page 530: ...A6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0 Initial value 0 0 1 1 1 1 1 1 R W R W R W R W R W R W R W R W R W MSTPCRA is an 8 bit readable writable register that performs module stop mode control When the MSTPA3 bit in MSTPCRA is set to 1 PPG operation stops at the end of the bus cycle and a transition is made to module stop mode Registers cannot be read or written to in module stop mode For deta...

Page 531: ...ns Output trigger signal Pulse output pin Internal data bus Normal output inverted output C PODR Q D NDER Q NDR Q D DDR Q Figure 12 2 PPG Output Operation Table 12 3 PPG Operating Conditions NDER DDR Pin Function 0 0 Generic input port 1 Generic output port 1 0 Generic input port but the PODR bit is a read only bit and when compare match occurs the NDR bit value is transferred to the PODR bit 1 PP...

Page 532: ...he specified compare match event occurs Figure 12 3 shows the timing of these operations for the case of normal output in groups 2 and 3 triggered by compare match A TCNT N N 1 ø TGRA N Compare match A signal NDRH m n PODRH PO8 to PO15 n m n Figure 12 3 Timing of Transfer and Output of NDR Contents Example ...

Page 533: ...compare register with output disabled 2 Set the PPG output trigger period 3 Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clear source with bits CCLR1 and CCLR0 4 Enable the TGIA interrupt in TIER The DTC or DMAC can also be set up to transfer data to NDR 5 Set the initial output values in PODR 6 Set the DDR and NDER bits for the pins to be used for pulse outpu...

Page 534: ...TGIEA bit in TIER to 1 to enable the compare match A TGIA interrupt 2 Write H F8 in P1DDR and NDERH and set the G3CMS1 G3CMS0 G2CMS1 and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger Write output data H 80 in NDRH 3 The timer counter in the TPU channel starts When compare match A occurs the NDRH contents are transferred to PODRH ...

Page 535: ...disabled 2 Set the pulse output trigger period in TGRB and the non overlap margin in TGRA 3 Select the counter clock source with bits TPSC2 to TPSC0 in TCR Select the counter clear source with bits CCLR1 and CCLR0 4 Enable the TGIA interrupt in TIER The DTC or DMAC can also be set up to transfer data to NDR 5 Set the initial output values in PODR 6 Set the DDR and NDER bits for the pins to be used...

Page 536: ...ample in which pulse output is used for four phase complementary non overlapping pulse output TCNT value TCNT TGRB TGRA H 0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 PODRH PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Non overlap margin Figure 12 7 Non Overlapping Pulse Output Example Four Phase Complementary ...

Page 537: ...er Set the G3NOV and G2NOV bits in PMR to 1 to select non overlapping output Write output data H 95 in NDRH 3 The timer counter in the TPU channel starts When a compare match with TGRB occurs outputs change from 1 to 0 When a compare match with TGRA occurs outputs change from 0 to 1 the change from 0 to 1 is delayed by the value set in TGRA The TGIA interrupt handling routine writes the next outpu...

Page 538: ...f the PODR contents can be output Figure 12 8 shows the outputs when G3INV and G2INV are cleared to 0 in addition to the settings of figure 12 7 TCNT value TCNT TGRB TGRA H 0000 NDRH 95 65 59 56 95 65 00 95 05 65 41 59 50 56 14 95 05 65 PODRL PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Time Figure 12 8 Inverted Pulse Output Example ...

Page 539: ...by compare match If TGRA functions as an input capture register in the TPU channel selected by PCR pulse output will be triggered by the input capture signal Figure 12 9 shows the timing of this output ø N M N TIOC pin Input capture signal NDR PODR M N PO Figure 12 9 Pulse Output Triggered by Input Capture Example ...

Page 540: ...ons in which the output trigger event will not occur Note on Non Overlapping Output During non overlapping operation the transfer of NDR bit values to PODR bits takes place as follows NDR bits are always transferred to PODR bits at compare match A At compare match B NDR bits are transferred only if their value is 0 Bits are not transferred if their value is 1 Figure 12 10 illustrates the non overl...

Page 541: ...handling routine write the next data in NDR or by having the TGIA interrupt activate the DTC or DMAC Note however that the next data must be written before the next compare match B occurs Figure 12 11 shows the timing of this operation 0 1 output 0 output 0 1 output 0 output Do not write to NDR here Write to NDR here Compare match A Compare match B NDR PODR Do not write to NDR here Write to NDR he...

Page 542: ... or by an external reset signal Timer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combination of two independent compare match signals enabling the timer to generate output waveforms with an arbitrary duty cycle or PWM output Provision for cascading of two channels Operation as a 16 bit timer is possible using channel 0 ch...

Page 543: ...ch A0 Clear 1 CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt signals TMO0 TMRI01 TMRI23 Internal bus TCORA0 Comparator A0 Comparator B0 TCORB0 TCSR0 TCR0 TCORA1 Comparator A1 TCNT1 Comparator B1 TCORB1 TCSR1 TCR1 TMCI01 TMCI23 TCNT0 Overflow 1 Overflow 0 Compare match B1 Compare match B0 TMO1 A D conversion start request signal Clock select Control logic Clear 0 Figure 13 1 Block Diagram of 8 Bit Tim...

Page 544: ...TMO1 Output Outputs at compare match Timer clock input pin 23 TMCI23 Input Inputs external clock for counter Timer reset input pin 23 TMRI23 Input Inputs external reset to counter 2 Timer output pin 2 TMO2 Output Outputs at compare match Timer clock input pin 23 TMCI23 Input Inputs external clock for counter Timer reset input pin 23 TMRI23 Input Inputs external reset to counter 3 Timer output pin ...

Page 545: ...control register 2 TCR2 R W H 00 H FDC0 Timer control status register 2 TCSR2 R W 2 H 00 H FDC2 Time constant register A2 TCORA2 R W H FF H FDC4 Time constant register B2 TCORB2 R W H FF H FDC6 Timer counter 2 TCNT2 R W H 00 H FDC8 3 Timer control register 3 TCR3 R W H 00 H FDC1 Timer control status register 3 TCSR3 R W 2 H 10 H FDC3 Time constant register A3 TCORA3 R W H FF H FDC5 Time constant r...

Page 546: ...ut or by a compare match signal Which signal is to be used for clearing is selected by clock clear bits CCLR1 and CCLR0 of TCR When a timer counter overflows from H FF to H 00 OVF in TCSR is set to 1 TCNT0 and TCNT1 are each initialized to H 00 by a reset and in hardware standby mode 13 2 2 Time Constant Registers A0 to A3 TCORA0 to TCORA3 15 1 R W 14 1 R W 13 1 R W 12 1 R W 11 1 R W 10 1 R W 9 1 ...

Page 547: ...pared with the value in TCNT When a match is detected the corresponding CMFB flag of TCSR is set Note however that comparison is disabled during the T2 state of a TCOR write cycle The timer output can be freely controlled by these compare match signals and the settings of output select bits OS3 and OS2 of TCSR TCORB0 and TCORB1 are each initialized to H FF by a reset and in hardware standby mode 1...

Page 548: ...ests CMIA are disabled Initial value 1 CMFA interrupt requests CMIA are enabled Bit 5 Timer Overflow Interrupt Enable OVIE Selects whether OVF interrupt requests OVI are enabled or disabled when the OVF flag of TCSR is set to 1 Bit 5 OVIE Description 0 OVF interrupt requests OVI are disabled Initial value 1 OVF interrupt requests OVI are enabled Bits 4 and 3 Counter Clear 1 and 0 CCLR1 and CCLR0 T...

Page 549: ...ption 0 0 0 Clock input disabled Initial value 1 Internal clock counted at falling edge of ø 8 1 0 Internal clock counted at falling edge of ø 64 1 Internal clock counted at falling edge of ø 8192 1 0 0 For channel 0 count at TCNT1 overflow signal For channel 1 count at TCNT0 compare match A For channel 2 count at TCNT3 overflow signal For channel 3 count at TCNT2 compare match A 1 External clock ...

Page 550: ...6 CMFA 0 R W 5 OVF 0 R W 4 1 3 OS3 0 R W 0 OS0 0 R W 2 OS2 0 R W 1 OS1 0 R W Bit Initial value R W TCSR0 TCSR1 TCSR3 7 CMFB 0 R W 6 CMFA 0 R W 5 OVF 0 R W 4 0 R W 3 OS3 0 R W 0 OS0 0 R W 2 OS2 0 R W 1 OS1 0 R W Bit Initial value R W TCSR2 TCSR0 to TCSR3 are 8 bit registers that display compare match and overflow statuses and control compare match output TCSR0 and TCSR2 are initialized to H 00 and ...

Page 551: ...us flag indicating whether the values of TCNT and TCORA match Bit 6 CMFA Description 0 Clearing conditions Initial value Cleared by reading CMFA when CMFA 1 then writing 0 to CMFA When DTC is activated by CMIA interrupt while DISEL bit of MRB in DTC is 0 1 Setting condition Set when TCNT matches TCORA Bit 5 Timer Overflow Flag OVF Status flag indicating that TCNT has overflowed changed from H FF t...

Page 552: ...e match A on the output level and both of them can be controlled independently Note however that priorities are set such that toggle output 1 output 0 output If compare matches occur simultaneously the output changes according to the compare match with the higher priority Timer output is disabled when bits OS3 to OS0 are all 0 After a reset the timer output is 0 until the first compare match event...

Page 553: ...d a transition is made to module stop mode For details see section 24 5 Module Stop Mode MSTPCRA is initialized to H 3F by a power on reset and in hardware standby mode It is not initialized by a manual reset and in software standby mode Bit 4 Module Stop MSTPA4 Specifies the TMR0 and TMR1 module stop mode Bit 4 MSTPA4 Description 0 TMR0 TMR1 module stop mode cleared 1 TMR0 TMR1 module stop mode s...

Page 554: ...1 N N 1 Figure 13 2 Count Timing for Internal Clock Input External Clock Three incrementation methods can be selected by setting bits CKS2 to CKS0 in TCR at the rising edge the falling edge and both rising and falling edges Note that the external clock pulse width must be at least 1 5 states for incrementation at a single edge and at least 2 5 states for incrementation at both edges The counter wi...

Page 555: ... to 1 by a compare match signal generated when the TCOR and TCNT values match The compare match signal is generated at the last state in which the match is true just before the timer counter is updated Therefore when TCOR and TCNT match the compare match signal is not generated until the next incrementation clock input Figure 13 4 shows this timing ø TCNT N N 1 TCOR N Compare match signal CMF Figu...

Page 556: ... shows the timing when the output is set to toggle at compare match A ø Compare match A signal Timer output pin Figure 13 5 Timing of Timer Output Timing of Compare Match Clear The timer counter is cleared when compare match A or B occurs depending on the setting of the CCLR1 and CCLR0 bits in TCR Figure 13 6 shows the timing of this operation ø N H 00 Compare match signal TCNT Figure 13 6 Timing ...

Page 557: ...least 1 5 states Figure 13 7 shows the timing of this operation ø Clear signal External reset input pin TCNT N H 00 N 1 Figure 13 7 Timing of External Reset 13 3 4 Timing of Overflow Flag OVF Setting The OVF in TCSR is set to 1 when the timer count overflows changes from H FF to H 00 Figure 13 8 shows the timing of this operation ø OVF Overflow signal TCNT H FF H 00 Figure 13 8 Timing of OVF Setti...

Page 558: ...hen a 16 bit compare match event occurs The 16 bit counter TCNT0 and TCNT1 TCNT2 and TCNT3 together is cleared even if counter clear by the TMRI01 TMRI23 pin has also been set The settings of the CCLR1 and CCLR0 bits in TCR1 and TCR3 are ignored The lower 8 bits cannot be cleared independently Pin output Control of output from the TMO0 TMO2 pin by bits OS3 to OS0 in TCSR0 TCSR2 is in accordance wi...

Page 559: ...A1 Interrupt by CMFA Possible CMIB1 Interrupt by CMFB Possible OVI1 Interrupt by OVF Not possible 2 CMIA2 Interrupt by CMFA Possible CMIB2 Interrupt by CMFB Possible OVI2 Interrupt by OVF Not possible 3 CMIA3 Interrupt by CMFA Possible CMIB3 Interrupt by CMFB Possible OVI3 Interrupt by OVF Not possible Low Note This table shows the initial state immediately after a reset The relative channel prior...

Page 560: ...he timer counter is cleared when its value matches the constant in TCORA 2 In TCSR bits OS3 to OS0 are set to B 0110 causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match With these settings the 8 bit timer provides output of pulses at a rate determined by TCORA with a pulse width determined by TCORB No software intervention is required TCNT H FF Counter clea...

Page 561: ...ar If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle the clear takes priority so that the counter is cleared and the write is not performed Figure 13 10 shows this operation ø Address TCNT address Internal write signal Counter clear signal TCNT N H 00 T1 T2 TCNT write cycle by CPU Figure 13 10 Contention between TCNT Write and Clear ...

Page 562: ... the T2 state of a TCNT write cycle the write takes priority and the counter is not incremented Figure 13 11 shows this operation ø Address TCNT address Internal write signal TCNT input clock TCNT N M T1 T2 TCNT write cycle by CPU Counter write data Figure 13 11 Contention between TCNT Write and Increment ...

Page 563: ...priority and the compare match signal is disabled even if a compare match event occurs Figure 13 12 shows this operation ø Address TCOR address Internal write signal TCNT TCOR N M T1 T2 TCOR write cycle by CPU TCOR write data N N 1 Compare match signal Disabled Figure 13 12 Contention between TCOR Write and Compare Match ...

Page 564: ... may increment erroneously when the internal clock is switched over Table 13 5 shows the relationship between the timing at which the internal clock is switched by writing to the CKS1 and CKS0 bits and the TCNT operation When the TCNT clock is generated from an internal clock the falling edge of the internal clock pulse is detected If clock switching causes a change from high to low level as shown...

Page 565: ...tching from low to low 1 Clock before switchover Clock after switchover TCNT clock TCNT CKS bit write N N 1 2 Switching from low to high 2 Clock before switchover Clock after switchover TCNT clock TCNT CKS bit write N N 1 N 2 3 Switching from high to low 3 Clock before switchover Clock after switchover TCNT clock TCNT CKS bit write N N 1 N 2 4 ...

Page 566: ... stop to low 2 Includes switching from stop to high 3 Includes switching from high to stop 4 Generated on the assumption that the switchover is a falling edge TCNT is incremented 13 6 6 Interrupts and Module Stop Mode If module stop mode is entered when an interrupt has been requested it will not be possible to clear the CPU interrupt source or DMAC and DTC activation source Interrupts should ther...

Page 567: ...rol register DACR 14 1 1 Features The features of the 14 bit PWM D A are listed below The pulse is subdivided into multiple base cycles to reduce ripple Two resolution settings and two base cycle settings are available The resolution can be set equal to one or two system clock cycles The base cycle can be set equal to T 64 or T 256 where T is the resolution Four operating rates The two resolution ...

Page 568: ...PWM D A data register A 15 bits DADRB PWM D A data register B 15 bits DACNT PWM D A counter 14 bits Control logic Clock selection Clock Internal data bus Basic cycle compare match A Fine adjustment pulse addition A Basic cycle compare match B Fine adjustment pulse addition B Basic cycle overflow Comparator A Comparator B Bus interface Module data bus Figure 14 1 PWM D A Block Diagram ...

Page 569: ...WM D A data register AL0 DADRAL0 R W H FF H FDB9 2 PWM D A data register BH0 DADRBH0 R W H FF H FDBA 2 PWM D A data register BL0 DADRBL0 R W H FF H FDBB 2 PWM D A counter H0 DACNTH0 R W H 00 H FDBA 2 PWM D A counter L0 DACNTL0 R W H 03 H FDBB 2 1 PWM D A control register 1 DACR1 R W H 30 H FDBC 2 PWM D A data register AH1 DADRAH1 R W H FF H FDBC 2 PWM D A data register AL1 DADRAL1 R W H FF H FDBD ...

Page 570: ... Master Interface for details DACNT functions as the time base for both PWM D A channels When a channel operates with 14 bit precision it uses all DACNT bits When a channel operates with 12 bit precision it uses the lower 12 counter bits and ignores the upper two counter bits DACNT is initialized to H 0003 by a reset in the standby modes watch mode subactive mode subsleep mode and module stop mode...

Page 571: ... See section 14 3 Bus Master Interface for details The least significant CPU bit of DADRA is not used and is always read as 1 DADR is initialized to H FFFF by a reset and in the standby modes watch mode subactive mode subsleep mode and module stop mode Bits 15 to 3 PWM D A Data 13 to 0 DA13 to DA0 The digital value to be converted to an analog value is set in the upper 14 bits of the PWM D A data ...

Page 572: ...an be accessed The REGS bit can be accessed regardless of whether DADRB or DACNT is selected Bit 0 REGS Description 0 DADRA and DADRB can be accessed 1 DACR and DACNT can be accessed Initial value 14 2 3 PWM D A Control Register DACR 7 TEST 0 R W 6 PWME 0 R W 5 1 4 1 3 OEB 0 R W 0 CKS 0 R W 2 OEA 0 R W 1 OS 0 R W Bit Initial value R W DACR is an 8 bit readable writable register that selects test m...

Page 573: ...ese bits cannot be modified and are always read as 1 Bit 3 Output Enable B OEB Enables or disables output on PWM D A channel B Bit 3 OEB Description 0 PWM D A channel B output at the PWM1 PWM3 pin is disabled Initial value 1 PWM D A channel B output at the PWM1 PWM3 pin is enabled Bit 2 Output Enable A OEA Enables or disables output on PWM D A channel A Bit 2 OEA Description 0 PWM D A channel A ou...

Page 574: ...ntrol When the MSTPB2 is set to 1 at the end of the bus cycle 14 bit PWM timer 0 operation is halted and a transition made to module stop mode When the MSTPB1 is set to 1 at the end of the bus cycle PWM timer 1 operation is halted and a transition made to module stop mode See 24 5 Module Stop Mode for details MSTPCRB is initialized to H FF by a power on reset and in hardware standby mode It is not...

Page 575: ...MP Next when the lower byte is read the lower byte value in TEMP is transferred to the CPU These registers should always be accessed 16 bits at a time by word access or two consecutive byte accesses and the upper byte should always be accessed before the lower byte Correct data will not be transferred if only the upper byte or only the lower byte is accessed Figure 14 2 shows the data flow for acc...

Page 576: ...us interface Module data bus Upper Byte Write TEMP H AA DACNTL DACNTH CPU H 57 Lower byte Bus interface Module data bus Lower Byte Write TEMP H AA DACNTL H 57 DACNTH H AA Figure 14 2 a Access to DACNT CPU Writes H AA57 to DACNT ...

Page 577: ...us interface Module data bus Upper Byte Read TEMP H 57 DACNTL H 57 DACNTH H AA CPU H 57 Lower byte Bus interface Module data bus Lower Byte Read TEMP H 57 DACNTL DACNTH Figure 14 2 b Access to DACNT CPU Reads H AA57 from DACNT ...

Page 578: ...available tf tL TL tLn when OS 0 m n 1 1 conversion cycle T 214 16384 Basic cycle T 64 or T 256 T Resolution When CFS 0 m 256 when CFS 1 m 64 Figure 14 3 PWM D A Operation Table 14 4 summarizes the relationships of the CKS CFS and OS bit settings to the resolution base cycle and conversion cycle The PWM output remains flat unless DADR contains at least a certain minimum value Table 14 4 indicates ...

Page 579: ...12 0 0 409 6 10 0 0 0 0 102 4 1 25 6 1638 4 1 Always low or high DADR H 0003 to H 00FF 14 1638 4 2 Data value T DADR H 0103 to H FFFF 12 0 0 409 6 10 0 0 0 0 102 4 1 0 2 0 12 8 3276 8 1 Always low or high DADR H 0001 to H 03FD 14 3276 8 2 Data value T DADR H 0401 to H FFFD 12 0 0 819 2 10 0 0 0 0 204 8 1 51 2 3276 8 1 Always low or high DADR H 0003 to H 00FF 14 3276 8 2 Data value T DADR H 0103 to...

Page 580: ...tf2 tf255 tf256 1 conversion cycle tf1 tf2 tf3 tf255 tf256 T 64 tL1 tL2 tL3 tL255 tL256 TL Figure 14 4 1 Output Waveform b CFS 1 base cycle resolution T 256 tL1 tL2 tL3 tL63 tL64 tf1 tf2 tf63 tf64 1 conversion cycle tf1 tf2 tf3 tf63 tf64 T 256 tL1 tL2 tL3 tL63 tL64 TL Figure 14 4 2 Output Waveform ...

Page 581: ...tf2 tf255 tf256 1 conversion cycle tf1 tf2 tf3 tf255 tf256 T 64 tH1 tH2 tH3 tH255 tH256 TH Figure 14 4 3 Output Waveform b CFS 1 base cycle resolution T 256 tH1 tH2 tH3 tH63 tH64 tf1 tf2 tf63 tf64 1 conversion cycle tf1 tf2 tf3 tf63 tf64 T 256 tH1 tH2 tH3 tH63 tH64 TH Figure 14 4 4 Output Waveform ...

Page 582: ...mer mode and interval timer mode WDTOVF output when in watchdog timer mode If the counter overflows the WDT outputs WDTOVF It is possible to select whether the LSI is internally reset or an NMI interrupt is generated at the same time This internal reset is effected by either a power on reset or a manual reset Interrupt generation when in interval timer mode If the counter overflows the WDT generat...

Page 583: ... ø 128 ø 512 ø 2048 ø 8192 ø 32768 ø 131072 Clock Clock select Internal clock sources Bus interface Module bus Legend TCSR TCNT RSTCSR Note Timer control status register Timer counter Reset control status register Internal bus WDT The type of internal reset signal depends on a register setting There are two alternative types of reset namely power on reset and manual reset Figure 15 1 a Block Diagr...

Page 584: ... select Internal clock Bus interface Internal bus Module bus TCSR TCNT Note An internal reset signal can be generated by setting the register The reset thus generated is a power on reset Timer control status register Timer counter WDT Legend Internal NMI Interrupt request signal øSUB 2 øSUB 4 øSUB 8 øSUB 16 øSUB 32 øSUB 64 øSUB 128 øSUB 256 Figure 15 1 b Block Diagram of WDT1 ...

Page 585: ...the reset signal Table 15 2 WDT Registers Address 1 Channel Name Abbreviation R W Initial Value Write 2 Read 0 Timer control status register 0 TCSR0 R W 3 H 18 H FF74 H FF74 Timer counter 0 TCNT0 R W H 00 H FF74 H FF75 Reset control status register RSTCSR R W 3 H 1F H FF76 H FF77 1 Timer control status register 1 TCSR1 R W 3 H 00 H FFA2 H FFA2 Timer counter 1 TCNT1 R W H 00 H FFA2 H FFA3 All Pin f...

Page 586: ...mode selected by the WT IT bit in TCSR TCNT is initialized to H 00 by a reset in hardware standby mode or when the TME bit is cleared to 0 It is not initialized in software standby mode Note TCNT is write protected by a password to prevent accidental overwriting For details see section 15 2 5 Notes on Register Access 15 2 2 Timer Control Status Register TCSR TCSR0 Bit 7 6 5 4 3 2 1 0 OVF WT IT TME...

Page 587: ...changes from H FF to H 00 When internal reset request generation is selected in watchdog timer mode OVF is cleared automatically by the internal reset Bit 6 Timer Mode Select WT IT Selects whether the WDT is used as a watchdog timer or interval timer When TCNT overflows WDT0 generates the WDTOVF signal when in watchdog timer mode or a WOVI interrupt request to the CPU when in interval timer mode W...

Page 588: ...ME Description 0 TCNT is initialized to H 00 and halted Initial value 1 TCNT counts WDT0 TCSR Bit 4 Reserved Bit This bit is always read as 1 and cannot be modified WDT1 TCSR Bit 4 Prescaler Select PSS This bit is used to select an input clock source for the TCNT of WDT1 See the descriptions of Clock Select 2 to 0 for details WDT1 TCSR Bit 4 PSS Description 0 The TCNT counts frequency division clo...

Page 589: ...elect 2 to 0 CKS2 to CKS0 These bits select one of eight internal clock sources obtained by dividing the system clock ø or subclock ø SUB for input to TCNT WDT0 Input Clock Select Description Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Clock Overflow Period where ø 25 MHz 0 0 0 ø 2 initial value 20 4 µs 1 ø 64 652 8 µs 1 0 ø 128 1 3 ms 1 ø 512 5 2 ms 1 0 0 ø 2048 20 9 ms 1 ø 8192 83 6 ms 1 0 ø 32768 334 2 ms...

Page 590: ... 1 0 ø 128 1 3 ms 1 ø 512 5 2 ms 1 0 0 ø 2048 20 9 ms 1 ø 8192 83 6 ms 1 0 ø 32768 334 2 ms 1 ø 131072 1 34 s 1 0 0 0 øSUB 2 15 6 ms 1 øSUB 4 31 3 ms 1 0 øSUB 8 62 5 ms 1 øSUB 16 125 ms 1 0 0 øSUB 32 250 ms 1 øSUB 64 500 ms 1 0 øSUB 128 1 s 1 øSUB 256 2 s Note An overflow period is the time interval between the start of counting up from H 00 on the TCNT and the occurrence of a TCNT overflow ...

Page 591: ... Register Access Bit 7 Watchdog Overflow Flag WOVF Indicates that TCNT has overflowed changed from H FF to H 00 during watchdog timer operation This bit is not set in interval timer mode Bit 7 WOVF Description 0 Clearing condition Initial value Cleared by reading TCSR when WOVF 1 then writing 0 to WOVF 1 Setting condition Set when TCNT overflows changed from H FF to H 00 during watchdog timer oper...

Page 592: ...36 0 R W 5 BUZZE 0 R W 4 LCASS 0 R W 3 AE3 1 0 R W 0 AE0 1 0 R W 2 AE2 1 0 R W 1 AE1 0 R W Bit Initial value R W PFCR is an 8 bit readable writable register that performs address output control in external expanded mode Only bit 5 is described here For details of the other bits see section 7 2 6 Pin Function Control Register PFCR Bit 5 BUZZ Output Enable BUZZE Enables or disables BUZZ output from ...

Page 593: ...Figure 15 2 shows the format of data written to TCNT and TCSR TCNT and TCSR both have the same write address For a write to TCNT the upper byte of the written word must contain H 5A and the lower byte must contain the write data For a write to TCSR the upper byte of the written word must contain H A5 and the lower byte must contain the write data This transfers the write data from the lower byte t...

Page 594: ...o 0 but has no effect on the RSTE and RSTS bits To write to the RSTE and RSTS bits the upper byte must contain H 5A and the lower byte must contain the write data This writes the values in bits 6 and 5 of the lower byte into the RSTE and RSTS bits but has no effect on the WOVF bit H A5 H 00 15 8 7 0 H 5A Write data 15 8 7 0 Writing 0 to WOVF bit Writing to RSTE and RSTS bits Address H FF76 Address...

Page 595: ... resets the H8S 2633 Series internally is generated at the same time as the WDTOVF signal This reset can be selected as a power on reset or a manual reset depending on the setting of the RSTS bit in RSTCSR The internal reset signal is output for 518 states If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow the RES pin reset has priority a...

Page 596: ...o 0 Overflow WDTOVF and internal reset are generated WOVF 1 Timer mode select bit Timer enable bit Legend Figure 15 4 a WDT0 Watchdog Timer Operation TCNT value H 00 Time H FF WT IT 1 TME 1 Write H 00 to TCNT WT IT 1 TME 1 Write H 00 to TCNT 515 516 states Internal reset signal WT IT TME Overflow Occurrence of internal reset WOVF 1 Timer Mode Select bit Timer Enable bit Note The WOVF bit is set to...

Page 597: ...H 00 Time H FF WT IT 0 TME 1 WOVI Overflow Overflow Overflow Overflow Legend WOVI Interval timer interrupt request generation WOVI WOVI WOVI Figure 15 5 Interval Timer Operation 15 3 3 Timing of Setting Overflow Flag OVF The OVF flag is set to 1 if TCNT overflows during interval timer operation At the same time an interval timer interrupt WOVI is requested This timing is shown in figure 15 6 With ...

Page 598: ... watchdog timer operation At the same time the WDTOVF signal goes low If TCNT overflows while the RSTE bit in RSTCSR is set to 1 an internal reset signal is generated for the entire H8S 2633 Series chip Figure 15 7 shows the timing in this case ø TCNT H FF H 00 Overflow signal internal signal WOVF WDTOVF signal Internal reset signal 132 states 518 states WDT0 515 516 states WDT1 Figure 15 7 Timing...

Page 599: ...watchdog timer mode an NMI request is generated when a TCNT overflow occurs 15 5 Usage Notes 15 5 1 Contention between Timer Counter TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle the write takes priority and the timer counter is not incremented Figure 15 8 shows this operation Address ø Internal write signal TCNT input clock TCNT N M...

Page 600: ...is input to the RES pin of the H8S 2633 Series the H8S 2633 Series will not be initialized correctly Make sure that the WDTOVF signal is not input logically to the RES pin To reset the entire system by means of the WDTOVF signal use the circuit shown in figure 15 9 Reset input Reset signal to entire system H8S 2633 Series RES WDTOVF Figure 15 9 Circuit for System Reset by WDTOVF Signal Example 15 ...

Page 601: ...achieved character by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver Transmitter UART or Asynchronous Communication Interface Adapter ACIA A multiprocessor communication function is provided that enables serial data communication with a number of processors Choice of 12 serial data transfer formats Dat...

Page 602: ...e 7 bit data Note Descriptions in this section refer to LSB first transfer On chip baud rate generator allows any bit rate to be selected Choice of serial clock source internal clock from baud rate generator or external clock from SCK pin Four interrupt sources Four interrupt sources transmit data empty transmit end receive data full and receive error that can issue requests independently The tran...

Page 603: ...al data bus RxD TxD SCK Parity generation Parity check Clock External clock ø ø 4 ø 16 ø 64 TXI TEI RXI ERI SMR Legend RSR RDR TSR TDR SMR SCR SSR SCMR BRR Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Smart card mode register Bit rate register Figure 16 1 Block Diagram of SCI ...

Page 604: ...nsmit data pin 1 TxD1 Output SCI1 transmit data output 2 Serial clock pin 2 SCK2 I O SCI2 clock input output Receive data pin 2 RxD2 Input SCI2 receive data input Transmit data pin 2 TxD2 Output SCI2 transmit data output 3 Serial clock pin 3 SCK3 I O SCI3 clock input output Receive data pin 3 RxD3 Input SCI3 receive data input Transmit data pin 3 TxD3 Output SCI3 transmit data output 4 Serial cloc...

Page 605: ...ster 0 RDR0 R H 00 H FF7D 3 Smart card mode register 0 SCMR0 R W H F2 H FF7E 3 IrDA control register IrCR R W H 00 H FDB0 1 Serial mode register 1 SMR1 R W H 00 H FF80 3 Bit rate register 1 BRR1 R W H FF H FF81 3 Serial control register 1 SCR1 R W H 00 H FF82 3 Transmit data register 1 TDR1 R W H FF H FF83 3 Serial status register 1 SSR1 R W 2 H 84 H FF84 3 Receive data register 1 RDR1 R H 00 H FF...

Page 606: ...e register 4 BRR4 R W H FF H FDD9 Serial control register 4 SCR4 R W H 00 H FDDA Transmit data register 4 TDR4 R W H FF H FDDB Serial status register 4 SSR4 R W 2 H 84 H FDDC Receive data register 4 RDR4 R H 00 H FDDD Smart card mode register 4 SCMR4 R W H F2 H FDDE All Module stop control register B MSTPCRB R W H FF H FDE9 Module stop control register C MSTPCRC R W H FF H FDEA Notes 1 Lower 16 bi...

Page 607: ...ta Register RDR 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 0 0 R 2 0 R 1 0 R Bit Initial value R W RDR is a register that stores received serial data When the SCI has received one byte of serial data it transfers the received serial data from RSR to RDR where it is stored and completes the receive operation After this RSR is receive enabled Since RSR and RDR function as a double buffer in this way enables cont...

Page 608: ... set to 1 TSR cannot be directly read or written to by the CPU 16 2 4 Transmit Data Register TDR 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Bit Initial value R W TDR is an 8 bit register that stores data for serial transmission When the SCI detects that TSR is empty it transfers the transmit data written in TDR to TSR and starts serial transmission Continuous serial transmissi...

Page 609: ...y mode Bit 7 Communication Mode C A Selects asynchronous mode or clocked synchronous mode as the SCI operating mode Bit 7 C A Description 0 Asynchronous mode Initial value 1 Clocked synchronous mode Bit 6 Character Length CHR Selects 7 or 8 bits as the data length in asynchronous mode In clocked synchronous mode a fixed data length of 8 bits is used regardless of the CHR setting Bit 6 CHR Descript...

Page 610: ...he O E bit setting is only valid when the PE bit is set to 1 enabling parity bit addition and checking in asynchronous mode The O E bit setting is invalid in clocked synchronous mode when parity addition and checking is disabled in asynchronous mode and when a multiprocessor format is used Bit 4 O E Description 0 Even parity 1 Initial value 1 Odd parity 2 Notes 1 When even parity is set parity bit...

Page 611: ...ter before it is sent In reception only the first stop bit is checked regardless of the STOP bit setting If the second stop bit is 1 it is treated as a stop bit if it is 0 it is treated as the start bit of the next transmit character Bit 2 Multiprocessor Mode MP Selects multiprocessor format When multiprocessor format is selected the PE bit and O E bit parity settings are invalid The MP bit settin...

Page 612: ...lue R W SCR is a register that performs enabling or disabling of SCI transfer operations serial clock output in asynchronous mode and interrupt requests and selection of the serial clock source SCR can be read or written to by the CPU at all times SCR is initialized to H 00 by a reset and in standby mode Bit 7 Transmit Interrupt Enable TIE Enables or disables transmit data empty interrupt TXI requ...

Page 613: ... of serial transmission by the SCI Bit 5 TE Description 0 Transmission disabled 1 Initial value 1 Transmission enabled 2 Notes 1 The TDRE flag in SSR is fixed at 1 2 In this state serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0 SMR setting must be performed to decide the transfer format before setting the TE bit to 1 Bit 4 Receive Enable...

Page 614: ...ote When receive data including MPB 0 is received receive data transfer from RSR to RDR receive error detection and setting of the RDRF FER and ORER flags in SSR is not performed When receive data including MPB 1 is received the MPB bit in SSR is set to 1 the MPIE bit is cleared to 0 automatically and generation of RXI and ERI interrupts when the TIE and RIE bits in SCR are set to 1 and FER and OR...

Page 615: ...f clock source selection see table 16 9 in section 16 3 Operation Bit 1 Bit 0 CKE1 CKE0 Description 0 0 Asynchronous mode Internal clock SCK pin functions as I O port 1 Clocked synchronous mode Internal clock SCK pin functions as serial clock output 1 1 Asynchronous mode Internal clock SCK pin functions as clock output 2 Clocked synchronous mode Internal clock SCK pin functions as serial clock out...

Page 616: ...se flags they must be read as 1 beforehand The TEND flag and MPB flag are read only flags and cannot be modified SSR is initialized to H 84 by a reset in standby mode watch mode subactive mode and subsleep mode or module stop mode Bit 7 Transmit Data Register Empty TDRE Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR Bit 7 TDRE Description 0 ...

Page 617: ...mpleted while the RDRF flag is still set to 1 an overrun error will occur and the receive data will be lost Bit 5 Overrun Error ORER Indicates that an overrun error occurred during reception causing abnormal termination Bit 5 ORER Description 0 Clearing condition Initial value 1 When 0 is written to ORER after reading ORER 1 1 Setting condition When the next serial reception is completed while RDR...

Page 618: ...annot be continued while the FER flag is set to 1 In clocked synchronous mode serial transmission cannot be continued either Bit 3 Parity Error PER Indicates that a parity error occurred during reception using parity addition in asynchronous mode causing abnormal termination Bit 3 PER Description 0 Clearing condition Initial value 1 When 0 is written to PER after reading PER 1 1 Setting condition ...

Page 619: ...e MPB stores the multiprocessor bit in the receive data MPB is a read only bit and cannot be modified Bit 1 MPB Description 0 Clearing condition Initial value When data with a 0 multiprocessor bit is received 1 Setting condition When data with a 1 multiprocessor bit is received Note Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format Bit 0 Multiprocessor Bi...

Page 620: ...nerator operating clock selected by bits CKS1 and CKS0 in SMR BRR can be read or written to by the CPU at all times BRR is initialized to H FF by a reset and in standby mode As baud rate generator control is performed independently for each channel different values can be set for each channel Table 16 3 shows sample BRR settings in asynchronous mode and table 16 4 shows sample BRR settings in cloc...

Page 621: ...15 0 00 0 19 2 34 9600 0 6 2 48 0 7 0 00 0 9 2 34 19200 0 3 0 00 0 4 2 34 31250 0 1 0 00 0 2 0 00 38400 0 1 0 00 ø 3 6864 MHz ø 4 MHz ø 4 9152 MHz ø 5 MHz Bit Rate bit s n N Error n N Error n N Error n N Error 110 2 64 0 70 2 70 0 03 2 86 0 31 2 88 0 25 150 1 191 0 00 1 207 0 16 1 255 0 00 2 64 0 16 300 1 95 0 00 1 103 0 16 1 127 0 00 1 129 0 16 600 0 191 0 00 0 207 0 16 0 255 0 00 1 64 0 16 1200 ...

Page 622: ...00 0 11 0 00 0 12 0 16 31250 0 5 0 00 0 5 2 40 0 7 0 00 38400 0 4 2 34 0 4 0 00 0 5 0 00 ø 9 8304 MHz ø 10 MHz ø 12 MHz ø 12 288 MHz Bit Rate bit s n N Error n N Error n N Error n N Error 110 2 174 0 26 2 177 0 25 2 212 0 03 2 217 0 08 150 2 127 0 00 2 129 0 16 2 155 0 16 2 159 0 00 300 1 255 0 00 2 64 0 16 2 77 0 16 2 79 0 00 600 1 127 0 00 1 129 0 16 1 155 0 16 1 159 0 00 1200 0 255 0 00 1 64 0 ...

Page 623: ... 25 0 16 0 27 0 00 31250 0 13 0 00 0 14 1 70 0 15 0 00 0 16 1 20 38400 0 11 0 00 0 12 0 13 0 13 0 00 ø 18 MHz ø 19 6608 MHz ø 20 MHz ø 25 MHz Bit Rate bit s n N Error n N Error n N Error n N Error 110 3 79 0 12 3 86 0 31 3 88 0 25 3 110 0 02 150 2 233 0 16 2 255 0 00 3 64 0 16 3 80 0 47 300 2 116 0 16 2 127 0 00 2 129 0 16 2 162 0 15 600 1 233 0 16 1 255 0 00 2 64 0 16 2 80 0 47 1200 1 116 0 16 1 ...

Page 624: ... 155 5 k 0 99 0 199 1 99 1 124 1 199 1 249 2 77 10 k 0 49 0 99 0 199 0 249 1 99 1 124 1 155 25 k 0 19 0 39 0 79 0 99 0 159 0 199 0 249 50 k 0 9 0 19 0 39 0 49 0 79 0 99 0 124 100 k 0 4 0 9 0 19 0 24 0 39 0 49 0 62 250 k 0 1 0 3 0 7 0 9 0 15 0 19 0 24 500 k 0 0 0 1 0 3 0 4 0 7 0 9 1 M 0 0 0 1 0 3 0 4 2 5 M 0 0 0 1 5 M 0 0 Note As far as possible the setting should be made so that the error is no mo...

Page 625: ...bit s N BRR setting for baud rate generator 0 N 255 ø Operating frequency MHz n Baud rate generator input clock n 0 to 3 See the table below for the relation between n and the clock SMR Setting n Clock CKS1 CKS0 0 ø 0 0 1 ø 4 0 1 2 ø 16 1 0 3 ø 64 1 1 The bit rate error in asynchronous mode is found from the following formula Error ø 106 N 1 B 64 22n 1 1 100 ...

Page 626: ...us Mode ø MHz Maximum Bit Rate bit s n N 2 62500 0 0 2 097152 65536 0 0 2 4576 76800 0 0 3 93750 0 0 3 6864 115200 0 0 4 125000 0 0 4 9152 153600 0 0 5 156250 0 0 6 187500 0 0 6 144 192000 0 0 7 3728 230400 0 0 8 250000 0 0 9 8304 307200 0 0 10 312500 0 0 12 375000 0 0 12 288 384000 0 0 14 437500 0 0 14 7456 460800 0 0 16 500000 0 0 17 2032 537600 0 0 18 562500 0 0 19 6608 614400 0 0 20 625000 0 0...

Page 627: ...00 3 0 7500 46875 3 6864 0 9216 57600 4 1 0000 62500 4 9152 1 2288 76800 5 1 2500 78125 6 1 5000 93750 6 144 1 5360 96000 7 3728 1 8432 115200 8 2 0000 125000 9 8304 2 4576 153600 10 2 5000 156250 12 3 0000 187500 12 288 3 0720 192000 14 3 5000 218750 14 7456 3 6864 230400 16 4 0000 250000 17 2032 4 3008 268800 18 4 5000 281250 19 6608 4 9152 307200 20 5 0000 312500 25 6 2500 390625 ...

Page 628: ...ous Mode ø MHz External Input Clock MHz Maximum Bit Rate bit s 2 0 3333 333333 3 4 0 6667 666666 7 6 1 0000 1000000 0 8 1 3333 1333333 3 10 1 6667 1666666 7 12 2 0000 2000000 0 14 2 3333 2333333 3 16 2 6667 2666666 7 18 3 0000 3000000 0 20 3 3333 3333333 3 25 4 1667 4166666 7 ...

Page 629: ...or details of the other bits in SCMR see 17 2 1 Smart Card Mode Register SCMR SCMR is initialized to H F2 by a reset and in standby mode Bits 7 to 4 Reserved These bits are always read as 1 and cannot be modified Bit 3 Smart Card Data Transfer Direction SDIR Selects the serial parallel conversion format This bit is valid when 8 bit data is used as the transmit receive format Bit 3 SDIR Description...

Page 630: ...ode Select SMIF When the smart card interface operates as a normal SCI 0 should be written in this bit Bit 0 SMIF Description 0 Operates as normal SCI smart card interface function disabled Initial value 1 Smart card interface function enabled 16 2 10 IrDA Control Register IrCR Bit 7 6 5 4 3 2 1 0 IrE IrCKS2 IrCKS1 IrCKS0 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W IrCR is an 8 bit read writ...

Page 631: ...ontrol Registers B and C MSTPCRB MSTPCRC 7 MSTPB7 1 R W 6 MSTPB6 1 R W 5 MSTPB5 1 R W 4 MSTPB4 1 R W 3 MSTPB3 1 R W 0 MSTPB0 1 R W 2 MSTPB2 1 R W 1 MSTPB1 1 R W Bit Initial value R W MSTPCRB 7 MSTPC7 1 R W 6 MSTPC6 1 R W 5 MSTPC5 1 R W 4 MSTPC4 1 R W 3 MSTPC3 1 R W 0 MSTPC0 1 R W 2 MSTPC2 1 R W 1 MSTPC1 1 R W Bit Initial value R W MSTPCRC MSTPCRB and MSTPCRC are 8 bit readable writable registers t...

Page 632: ... Initial value Bit 6 Module Stop MSTPB6 Specifies the SCI1 module stop mode Bit 6 MSTPB6 Description 0 SCI1 module stop mode is cleared 1 SCI1 module stop mode is set Initial value Bit 5 Module Stop MSTPB5 Specifies the SCI2 module stop mode Bit 5 MSTPB5 Description 0 SCI2 module stop mode is cleared 1 SCI2 module stop mode is set Initial value 2 Module Stop Control Register C MSTPCRC Bit 7 Module...

Page 633: ... in SCR as shown in table 16 9 Asynchronous Mode Data length Choice of 7 or 8 bits Choice of parity addition multiprocessor bit addition and addition of 1 or 2 stop bits the combination of these parameters determines the transfer format and character length Detection of framing parity and overrun errors and breaks during reception Choice of internal or external clock as SCI clock source When inter...

Page 634: ... Serial Transfer Format Selection SMR Settings SCI Transfer Format Bit 7 Bit 6 Bit 2 Bit 5 Bit 3 Data Multi Processor Parity Stop Bit C A CHR MP PE STOP Mode Length Bit Bit Length 0 0 0 0 0 Asynchronous 8 bit data No No 1 bit 1 mode 2 bits 1 0 Yes 1 bit 1 2 bits 1 0 0 7 bit data No 1 bit 1 2 bits 1 0 Yes 1 bit 1 2 bits 0 1 0 Asynchronous mode multi 8 bit data Yes No 1 bit 1 processor format 2 bits...

Page 635: ...it 0 Clock C A CKE1 CKE0 Mode Source SCK Pin Function 0 0 0 Asynchronous Internal SCI does not use SCK pin 1 mode Outputs clock with same frequency as bit rate 1 0 External Inputs clock with frequency of 16 times 1 the bit rate 1 0 0 Clocked synchronous Internal Outputs serial clock 1 mode 1 0 External Inputs serial clock 1 ...

Page 636: ...sually held in the mark state high level The SCI monitors the transmission line and when it goes to the space state low level recognizes a start bit and starts serial communication One serial communication character consists of a start bit low level followed by data in LSB first order a parity bit high or low level and finally stop bits high level In asynchronous mode the SCI performs synchronizat...

Page 637: ...t data STOP S 8 bit data STOP STOP S 8 bit data P STOP S 7 bit data STOP P S 8 bit data MPB STOP S 8 bit data MPB STOP STOP S 7 bit data STOP MPB S 7 bit data STOP MPB STOP S 7 bit data STOP STOP CHR 0 0 0 0 1 1 1 1 0 0 1 1 MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 SMR Settings 1 2 3 4 5 6 7 8 9 10 11 12 Serial Transfer Format and Frame Length STOP S 8 bit data P STOP S 7 bit data ST...

Page 638: ...ransmit data as shown in figure 16 3 0 1 frame D0 D1 D2 D3 D4 D5 D6 D7 0 1 1 1 Figure 16 3 Relation between Output Clock and Transfer Data Phase Asynchronous Mode Data Transfer Operations SCI initialization asynchronous mode Before transmitting and receiving data you should first clear the TE and RE bits in SCR to 0 then initialize the SCI as described below When the operating mode transfer format...

Page 639: ...k selection in SCR Be sure to clear bits RIE TIE TEIE and MPIE and bits TE and RE to 0 When the clock is selected in asynchronous mode it is output immediately after SCR settings are made 2 Set the data transfer format in SMR and SCMR 3 Write a value corresponding to the bit rate to BRR Not necessary if an external clock is used 4 Wait at least one bit interval then set the TE bit or RE bit in SCR...

Page 640: ...1s is output and transmission is enabled 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission continuation procedure To continue serial transmission read 1 from the TDRE flag to confirm that writing is possible then write data to TDR and then clear the TDRE flag to 0 Checking ...

Page 641: ...ssor bit One parity bit even or odd parity or one multiprocessor bit is output A format in which neither a parity bit nor a multiprocessor bit is output can also be selected d Stop bit s One or two 1 bits stop bits are output e Mark state 1 is output continuously until the start bit that starts the next transmission is sent 3 The SCI checks the TDRE flag at the timing for sending the stop bit If t...

Page 642: ...ity bit Stop bit Start bit Data Parity bit Stop bit TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine TEI interrupt request generated Idle state mark state TXI interrupt request generated Figure 16 6 Example of Operation in Transmission in Asynchronous Mode Example with 8 Bit Data Parity One Stop Bit ...

Page 643: ...ror After performing the appropriate error processing ensure that the ORER PER and FER flags are all cleared to 0 Reception cannot be resumed if any of these flags are set to 1 In the case of a framing error a break can be detected by reading the value of the input port corresponding to the RxD pin SCI status check and receive data read Read SSR and check that RDRF 1 then read the receive data in ...

Page 644: ...or processing Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing No Yes Overrun error processing ORER 1 FER 1 Break PER 1 Clear RE bit in SCR to 0 Figure 16 7 Sample Serial Reception Data Flowchart cont ...

Page 645: ...ly the first is checked c Status check The SCI checks whether the RDRF flag is 0 indicating that the receive data can be transferred from RSR to RDR If all the above checks are passed the RDRF flag is set to 1 and the receive data is stored in RDR If a receive error is detected in the error check the operation is as shown in table 16 11 Note Subsequent receive operations cannot be performed when a...

Page 646: ... received data differs from the parity even or odd set in SMR Receive data is transferred from RSR to RDR Figure 16 8 shows an example of the operation for reception in asynchronous mode RDRF FER 0 1 frame D0 D1 D7 0 1 1 0 D0 D1 D7 0 1 0 1 1 Data Start bit Parity bit Stop bit Start bit Data Parity bit Stop bit RXI interrupt request generated ERI interrupt request generated by framing error Idle st...

Page 647: ...st sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added It then sends transmit data as data with a 0 multiprocessor bit added The receiving station skips the data until data with a 1 multiprocessor bit is sent When data with a 1 multiprocessor bit is received the receiving station compares that data with its own ID The ...

Page 648: ...mission to receiving station specified by ID MPB 1 MPB 0 H 01 H AA Legend MPB Multiprocessor bit Figure 16 9 Example of Inter Processor Communication Using Multiprocessor Format Transmission of Data H AA to Receiving Station A Data Transfer Operations Multiprocessor serial data transmission Figure 16 10 shows a sample flowchart for multiprocessor serial data transmission The following procedure sh...

Page 649: ...ck that the TDRE flag is set to 1 then write transmit data to TDR Set the MPBT bit in SSR to 0 or 1 Finally clear the TDRE flag to 0 Serial transmission continuation procedure To continue serial transmission be sure to read 1 from the TDRE flag to confirm that writing is possible then write data to TDR and then clear the TDRE flag to 0 Checking and clearing of the TDRE flag is automatic when the D...

Page 650: ...bit data is output in LSB first order c Multiprocessor bit One multiprocessor bit MPBT value is output d Stop bit s One or two 1 bits stop bits are output e Mark state 1 is output continuously until the start bit that starts the next transmission is sent 3 The SCI checks the TDRE flag at the timing for sending the stop bit If the TDRE flag is cleared to 0 data is transferred from TDR to TSR the st...

Page 651: ...erated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine TEI interrupt request generated Idle state mark state TXI interrupt request generated Figure 16 11 Example of SCI Operation in Transmission Example with 8 Bit Data Multiprocessor Bit One Stop Bit Multiprocessor serial data reception Figure 16 12 shows a sample flowchart for multiprocessor serial reception The fo...

Page 652: ...e RDRF flag is set to 1 then read the receive data in RDR and compare it with this station s ID If the data is not this station s ID set the MPIE bit to 1 again and clear the RDRF flag to 0 If the data is this station s ID clear the RDRF flag to 0 SCI status check and data reception Read SSR and check that the RDRF flag is set to 1 then read the data in RDR Receive error processing and break detec...

Page 653: ... Yes No Clear ORER PER and FER flags in SSR to 0 No Yes No Yes Framing error processing Overrun error processing ORER 1 FER 1 Break Clear RE bit in SCR to 0 5 Figure 16 12 Sample Multiprocessor Serial Reception Flowchart cont ...

Page 654: ...st is not generated and RDR retains its state ID1 a Data does not match station s ID MPIE RDR value 0 D0 D1 D7 1 1 0 D0 D1 D7 0 1 1 1 Data ID2 Start bit MPB Stop bit Start bit Data Data2 MPB Stop bit RXI interrupt request multiprocessor interrupt generated MPIE 0 Idle state mark state RDRF RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine Matches this station s ID so recept...

Page 655: ...mat in Synchronous Communication In clocked synchronous serial communication data on the transmission line is output from one falling edge of the serial clock to the next Data confirmation is guaranteed at the rising edge of the serial clock In clocked serial communication one character consists of data output starting with the LSB and ending with the MSB After the MSB is output the transmission l...

Page 656: ... clearing the RE bit to 0 does not change the contents of the RDRF PER FER and ORER flags or the contents of RDR Figure 16 15 shows a sample SCI initialization flowchart Wait Transfer start Note In simultaneous transmit and receive operations the TE and RE bits should both be cleared to 0 or set to 1 simultaneously Start initialization Set data transfer format in SMR and SCMR No Yes Set value in B...

Page 657: ...TxD pin is automatically designated as the transmit data output pin 2 SCI status check and transmit data write Read SSR and check that the TDRE flag is set to 1 then write transmit data to TDR and clear the TDRE flag to 0 3 Serial transmission continuation procedure To continue serial transmission be sure to read 1 from the TDRE flag to confirm that writing is possible then write data to TDR and t...

Page 658: ...bit 7 3 The SCI checks the TDRE flag at the timing for sending the MSB bit 7 If the TDRE flag is cleared to 0 data is transferred from TDR to TSR and serial transmission of the next frame is started If the TDRE flag is set to 1 the TEND flag in SSR is set to 1 the MSB bit 7 is sent and the TxD pin maintains its state If the TEIE bit in SCR is set to 1 at this time a TEI interrupt request is genera...

Page 659: ...ng procedure should be used for serial data reception When changing the operating mode from asynchronous to clocked synchronous be sure to check that the ORER PER and FER flags are all cleared to 0 The RDRF flag will not be set if the FER or PER flag is set to 1 and neither transmit nor receive operations will be possible ...

Page 660: ... resumed if the ORER flag is set to 1 SCI status check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt Serial reception continuation procedure To continue serial reception before the MSB bit 7 of the current frame is received fini...

Page 661: ... 1 when the RDRF flag changes to 1 a receive data full interrupt RXI request is generated Also if the RIE bit in SCR is set to 1 when the ORER flag changes to 1 a receive error interrupt ERI request is generated Figure 16 19 shows an example of SCI operation in reception Bit 7 Serial data Serial clock 1 frame RDRF ORER Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RXI interrupt request generated RDR data re...

Page 662: ...receive error occurs read the ORER flag in SSR and after performing the appropriate error processing clear the ORER flag to 0 Transmission reception cannot be resumed if the ORER flag is set to 1 SCI status check and receive data read Read SSR and check that the RDRF flag is set to 1 then read the receive data in RDR and clear the RDRF flag to 0 Transition of the RDRF flag from 0 to 1 can also be ...

Page 663: ...on for automatically varying the transfer rate The transfer rate must be varied using software IrDA Pulse encoder Pulse decoder IrCR TxD0 IrTxD RxD0 IrRxD SCI0 TxD RxD Figure 16 21 IrDA Block Diagram 1 Transmission When transmitting the signal UART frame output from the SCI is converted by the IrDA interface into an IR frame see Figure 16 22 When the value of the serial data is 0 a High pulse that...

Page 664: ...frame data is converted into UART frames by the IrDA interface and input to the SCI When a High pulse is detected 0 is output If there is no pulse for the duration of 1 bit 1 is output Pulses of less than the minimum pulse width of 1 41 µs are also recognized as 0 data 3 Selecting High Pulse Width Table 16 12 shows the settings of IrCKS2 to IrCKS0 for the minimum pulse width at various LSI operati...

Page 665: ...1 011 011 011 011 011 6 100 100 100 100 100 100 6 144 100 100 100 100 100 100 7 3728 100 100 100 100 100 100 8 100 100 100 100 100 100 9 8304 100 100 100 100 100 100 10 100 100 100 100 100 100 12 101 101 101 101 101 101 12 288 101 101 101 101 101 101 14 101 101 101 101 101 101 14 7456 101 101 101 101 101 101 16 101 101 101 101 101 101 16 9344 101 101 101 101 101 101 17 2032 101 101 101 101 101 101...

Page 666: ...TEND flag in SSR is set to 1 a TEI interrupt request is generated A TXI interrupt can activate the DMAC or DTC to perform data transfer The TDRE flag is cleared to 0 automatically when data transfer is performed by the DTC The DMAC or DTC cannot be activated by a TEI interrupt request When the RDRF flag in SSR is set to 1 an RXI interrupt request is generated When the ORER PER or FER flag in SSR i...

Page 667: ...ssible RXI Interrupt due to receive data full state RDRF Possible Not possible TXI Interrupt due to transmit data empty state TDRE Possible Not possible TEI Interrupt due to transmission end TEND Not possible Not possible 3 ERI Interrupt due to receive error ORER FER or PER Not possible Not possible RXI Interrupt due to receive data full state RDRF Possible Not possible TXI Interrupt due to transm...

Page 668: ... is written to TDR when the TDRE flag is cleared to 0 the data stored in TDR will be lost since it has not yet been transferred to TSR It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time the state of the status flags in SSR is as shown i...

Page 669: ...n are first set to 1 To send a break during serial transmission first clear DR to 0 then clear the TE bit to 0 When the TE bit is cleared to 0 the transmitter is initialized regardless of the current transmission state the TxD pin becomes an I O port and 0 is output from the TxD pin Receive Error Flags and Transmit Operations Clocked Synchronous Mode Only Transmission cannot be started when a rece...

Page 670: ...y formula 1 below M 0 5 1 2N L 0 5 F D 0 5 N 1 F 100 Formula 1 Where M Reception margin N Ratio of bit rate to clock N 16 D Clock duty D 0 to 1 0 L Frame length L 9 to 12 F Absolute value of clock rate deviation Assuming values of F 0 and D 0 5 in formula 1 a reception margin of 46 875 is given by formula 2 below When D 0 5 and F 0 M 0 5 1 2 16 100 46 875 Formula 2 However this is only the compute...

Page 671: ...de software standby mode watch mode subactive mode or subsleep mode depend on the port settings and becomes high level output after the relevant mode is cleared If a transition is made during transmission the data being transmitted will be undefined When transmitting without changing the transmit mode after the relevant mode is cleared transmission can be started by setting TE to 1 again and perfo...

Page 672: ...ransition during reception Read TEND flag in SSR TE 0 Transition to software standby mode etc Exit from software standby mode etc Change operating mode No All data transmitted TEND 1 Yes Yes Yes Transmission No No 1 3 2 TE 1 Initialization Start of transmission 1 Data being transmitted is interrupt ed After exiting software standby mode etc normal CPU transmis sion is possible by setting TE to 1 r...

Page 673: ...om software standby Figure 16 26 Asynchronous Transmission Using Internal Clock Port input output Last TxD bit held High output Port input output Marking output Port input output SCI TxD output Port Port Note Initialized by software standby SCK output pin TE bit TxD output pin SCI TxD output Start of transmission End of transmission Transition to software standby Exit from software standby Figure ...

Page 674: ...software standby mode etc Change operating mode No RDRF 1 Yes Yes Reception No 1 2 RE 1 Initialization Start of reception 1 Receive data being received be comes invalid 2 Includes module stop mode watch mode subactive mode and sub sleep mode Figure 16 28 Sample Flowchart for Mode Transition during Reception ...

Page 675: ...1 0 CKE0 0 and TE 1 synchronous mode low level output occurs for one half cycle 1 End of serial data transmission 2 TE bit 0 3 C A bit 0 switchover to port output 4 Occurrence of low level output see figure 16 29 SCK port Data TE C A CKE1 CKE0 Bit 7 Bit 6 1 End of transmission 4 Low level output 3 C A 0 2 TE 0 Half cycle low level output Figure 16 29 Operation when Switching from SCK Pin Function ...

Page 676: ... 1 CKE1 0 CKE0 0 and TE 1 make the following settings in the order shown 1 End of serial data transmission 2 TE bit 0 3 CKE1 bit 1 4 C A bit 0 switchover to port output 5 CKE1 bit 0 SCK port Data TE C A CKE1 CKE0 Bit 7 Bit 6 1 End of transmission 3 CKE1 1 5 CKE1 0 4 C A 0 2 TE 0 High level outputTE Figure 16 30 Operation when Switching from SCK Pin Function to Port Pin Function Example of Preventi...

Page 677: ...s Asynchronous mode Data length 8 bits Parity bit generation and checking Transmission of error signal parity error in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported On chip baud rate generator allows any bit rate to be selected Three interrupt sources Three interrupt sources transmit data empty receive...

Page 678: ...tor Internal data bus RxD TxD SCK Parity generation Parity check Clock ø ø 4 ø 16 ø 64 TXI RXI ERI SMR Legend SCMR RSR RDR TSR TDR SMR SCR SSR BRR Smart Card mode register Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register Serial control register Serial status register Bit rate register Figure 17 1 Block Diagram of Smart Card Interface ...

Page 679: ... pin 1 RxD1 Input SCI1 receive data input Transmit data pin 1 TxD1 Output SCI1 transmit data output 2 Serial clock pin 2 SCK2 I O SCI2 clock input output Receive data pin 2 RxD2 Input SCI2 receive data input Transmit data pin 2 TxD2 Output SCI2 transmit data output 3 Serial clock pin 3 SCK3 I O SCI3 clock input output Receive data pin 3 RxD3 Input SCI3 receive data input Transmit data pin 3 TxD3 O...

Page 680: ...SSR0 R W 2 H 84 H FF7C Receive data register 0 RDR0 R H 00 H FF7D Smart card mode register 0 SCMR0 R W H F2 H FF7E 1 Serial mode register 1 SMR1 R W H 00 H FF80 Bit rate register 1 BRR1 R W H FF H FF81 Serial control register 1 SCR1 R W H 00 H FF82 Transmit data register 1 TDR1 R W H FF H FF83 Serial status register 1 SSR1 R W 2 H 84 H FF84 Receive data register 1 RDR1 R H 00 H FF85 Smart card mod...

Page 681: ...rt card mode register 3 SCMR3 R W H F2 H FDD6 4 Serial mode register 4 SMR4 R W H 00 H FDD8 Bit rate register 4 BRR4 R W H FF H FDD9 Serial control register 4 SCR4 R W H 00 H FDDA Transmit data register 4 TDR4 R W H FF H FDDB Serial status register 4 SSR4 R W 2 H 84 H FDDC Receive data register 4 RDR4 R H 00 H FDDD Smart card mode register 4 SCMR4 R W H F2 H FDDE All Module stop control MSTPCRB R ...

Page 682: ...able register that selects the Smart Card interface function SCMR is initialized to H F2 by a reset and in standby mode Bits 7 to 4 Reserved These bits are always read as 1 and cannot be modified Bit 3 Smart Card Data Transfer Direction SDIR Selects the serial parallel conversion format Bit 3 SDIR Description 0 TDR contents are transmitted LSB first Initial value Receive data is stored in RDR LSB ...

Page 683: ...ttings Bit 2 SINV Description 0 TDR contents are transmitted as they are Initial value Receive data is stored as it is in RDR 1 TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR Bit 1 Reserved This bit is always read as 1 and cannot be modified Bit 0 Smart Card Interface Mode Select SMIF Enables or disables the Smart Card interface function Bit 0 SMI...

Page 684: ...ister SSR Bit 4 Error Signal Status ERS In Smart Card interface mode bit 4 indicates the status of the error signal sent back from the receiving end in transmission Framing errors are not detected in Smart Card interface mode Bit 4 ERS Description 0 Normal reception with no error signal Clearing conditions Initial value Upon reset and in standby mode or module stop mode When 0 is written to ERS af...

Page 685: ...ons Upon reset and in standby mode or module stop mode When the TE bit in SCR is 0 and the ERS bit is also 0 When TDRE 1 and ERS 0 normal transmission 2 5 etu after transmission of a 1 byte serial character when GM 0 and BLK 0 When TDRE 1 and ERS 0 normal transmission 1 5 etu after transmission of a 1 byte serial character when GM 0 and BLK 1 When TDRE 1 and ERS 0 normal transmission 1 0 etu after...

Page 686: ... of setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is performed The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register SCR Bit 7 GM Description 0 Normal smart card interface mode operation Initial value TEND flag generation 12 5 etu 11 5 etu in block transfer mode after ...

Page 687: ...n detection and automatic data retransmission not performed TXI interrupt generated by TDRE flag TEND flag set 11 5 etu after start of transmission 11 0 etu in GSM mode Bits 3 and 2 Basic Clock Pulse 1 and 2 BCP1 BCP0 These bits specify the number of basic clock periods in a 1 bit transfer interval on the Smart Card interface Bit 3 Bit 2 BCP1 BCP0 Description 0 1 32 clock periods Initial value 0 6...

Page 688: ...1 and 0 CKE1 CKE0 These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin In smart card interface mode in addition to the normal switching between clock output enabling and disabling the clock output can be specified as to be fixed high or low SCMR SMR SCR Setting SMIF C A GM CKE1 CKE0 SCK Pin Function 0 See the SCI 1 0 0 0 Operates as port I O pin 1 ...

Page 689: ... transfer mode Only asynchronous communication is supported there is no clocked synchronous communication function 17 3 2 Pin Connections Figure 17 2 shows a schematic diagram of Smart Card interface related pin connections In communication with an IC card since both transmission and reception are carried out on a single data transmission line the TxD pin and RxD pin should be connected with the L...

Page 690: ...ent IC card Data line Clock line Reset line Figure 17 2 Schematic Diagram of Smart Card Interface Pin Connections Note If an IC card is not connected and the TE and RE bits are both set to 1 closed transmission reception is possible enabling self diagnosis to be carried out ...

Page 691: ...ng end and retransmission of the data is requested If an error signal is sampled during transmission the same data is retransmitted Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp When there is no parity error Transmitting station output Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp When a parity error occurs Transmitting station output DE Receiving station output Start bit Data bits Parity bit Error signal Legend Ds D0 to D7 Dp D...

Page 692: ...e again The signal line is pulled high again by a pull up resistor 5 If the transmitting station does not receive an error signal it proceeds to transmit the next data frame If it does receive an error signal however it returns to step 2 and retransmits the erroneous data 2 Block Transfer Mode The operation sequence in block transfer mode is as follows 1 When the data line in not in use it is in t...

Page 693: ...O E bit is cleared to 0 if the IC card is of the direct convention type and set to 1 if of the inverse convention type Bits CKS1 and CKS0 select the clock source of the on chip baud rate generator Bits BCP1 and BCP0 select the number of basic clock periods in a 1 bit transfer interval For details see section 17 3 5 Clock The BLK bit is cleared to 0 in normal smart card interface mode and set to 1 ...

Page 694: ...pe the logic 1 level corresponds to state Z and the logic 0 level to state A and transfer is performed in LSB first order The start character data above is H 3B The parity bit is 1 since even parity is stipulated for the Smart Card Inverse convention SDIR SINV O E 1 Ds D7 D6 D5 D4 D3 D2 D1 D0 Dp A Z Z A A A A A A Z Z Z State With the inverse convention type the logic 1 level corresponds to state A...

Page 695: ...y the bit rate and the setting of bits BCP1 and BCP0 B ø S 22n 1 N 1 106 Where N Value set in BRR 0 N 255 B Bit rate bit s ø Operating frequency MHz n See table 17 4 S Number of internal clocks in 1 bit period set by BCP1 and BCP0 Table 17 4 Correspondence between n and CKS1 CKS0 n CKS1 CKS0 0 0 0 1 1 2 1 0 3 1 Table 17 5 Examples of Bit Rate B bit s for Various BRR Settings When n 0 and S 372 ø M...

Page 696: ... 13 00 14 2848 16 00 18 00 20 00 25 00 bit s N Error N Error N Error N Error N Error N Error N Error N Error N Error 9600 0 0 00 1 30 1 25 1 8 99 1 0 00 1 12 01 2 15 99 2 6 60 3 12 49 Table 17 7 Maximum Bit Rate at Various Frequencies Smart Card Interface Mode when S 372 ø MHz Maximum Bit Rate bit s N n 7 1424 9600 0 0 10 00 13441 0 0 10 7136 14400 0 0 13 00 17473 0 0 14 2848 19200 0 0 16 00 21505...

Page 697: ...its in SMR Set the PE bit to 1 4 Set the SMIF SDIR and SINV bits in SCMR When the SMIF bit is set to 1 the TxD and RxD pins are both switched from ports to SCI pins and are placed in the high impedance state 5 Set the value corresponding to the bit rate in BRR 6 Set the CKE0 and CKE1 bits in SCR Clear the TIE RIE TE RE MPIE and TEIE bits to 0 If the CKE0 bit is set to 1 the clock is output from th...

Page 698: ...6 To end transmission clear the TE bit to 0 With the above processing interrupt servicing or data transfer by the DMAC or DTC is possible If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled a transmit data empty interrupt TXI request will be generated If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is...

Page 699: ... 0 Start transmission Start No No No Yes Yes Yes Yes No End Write data to TDR and clear TDRE flag in SSR to 0 Error processing Error processing TEND 1 All data transmitted TEND 1 ERS 0 ERS 0 Figure 17 4 Example of Transmission Processing Flow ...

Page 700: ...s been completed In case of normal transmission TEND flag is set In case of transmit error ERS flag is set Steps 2 and 3 above are repeated until the TEND flag is set I O signal line output Data 1 Data 1 Figure 17 5 Relation Between Transmit Operation and Internal Registers Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp I O data 12 5etu TXI TEND interrupt 11 0etu DE Guard time When GM 1 Legend Ds Start bit D0 to D...

Page 701: ...ther is set perform the appropriate receive error processing then clear both the ORER and the PER flag to 0 3 Repeat steps 2 and 3 until it can be confirmed that the RDRF flag is set to 1 4 Read the receive data from RDR 5 When receiving data continuously clear the RDRF flag to 0 and go back to step 2 6 To end reception clear the RE bit to 0 Initialization Read RDR and clear RDRF flag in SSR to 0 ...

Page 702: ...mode first confirm that the receive operation has been completed then start from initialization clearing RE bit to 0 and setting TE bit to 1 The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed When switching from transmit mode to receive mode first confirm that the transmit operation has been completed then start from initialization clearing T...

Page 703: ...ehand as a DMAC or DTC activation source the DMAC or DTC will be activated by the TXI request and transfer of the transmit data will be carried out The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DTC In the event of an error the SCI retransmits the same data automatically During this period TEND remains cleared to 0 and the DMAC is not activated Theref...

Page 704: ...ng to the SCK pin to the value for the fixed output state in software standby mode 2 Write 0 to the TE bit and RE bit in the serial control register SCR to halt transmit receive operation At the same time set the CKE1 bit to the value for the fixed output state in software standby mode 3 Write 0 to the CKE0 bit in SCR to halt the clock 4 Wait for one serial clock period During this interval clock ...

Page 705: ...e 1 Data Format The data format is 8 bits with parity There is no stop bit but there is a 2 bit 1 bit or more in reception error guard time Also except during transmission with start bit data bits and parity bit the transmission pins go to the high impedance state so the signal lines must be fixed high with a pull up resistor 2 Transmit Receive Clock Only an internal clock generated by the on chip...

Page 706: ...ples the falling edge of the start bit using the basic clock and performs internal synchronization Receive data is latched internally at the rising edge of the 16th 32nd 186th or 128th pulse of the basic clock Figure 17 10 shows the receive data sampling timing when using a clock of 372 times the transfer rate Internal basic clock 372 clocks 186 clocks Receive data RxD Synchro nization sampling ti...

Page 707: ...n the received parity bit is checked the PER bit in SSR is automatically set to 1 If the RIE bit in SCR is enabled at this time an ERI interrupt request is generated The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled 2 The RDRF bit in SSR is not set for a frame in which an error has occurred 3 If no error is found when the received parity bit is checked the PER bit...

Page 708: ...or signal indicating an abnormality is received 8 If an error signal is not sent back from the receiving end the ERS bit in SSR is not set 9 If an error signal is not sent back from the receiving end transmission of one frame including a retransfer is judged to have been completed and the TEND bit in SSR is set to 1 If the TIE bit in SCR is enabled at this time a TXI interrupt request is generated...

Page 709: ...ls the I2 C bus differs partly from the Philips configuration however Each I2 C bus interface channel uses only one data line SDA and one clock line SCL to transfer data saving board and connector space 18 1 1 Features Selection of addressing format or non addressing format I2 C bus format addressing format with acknowledge bit for master slave operation Serial format non addressing format without...

Page 710: ...y NMOS push pull outputs function as NMOS open drain outputs when the bus drive function is selected Two pins P33 SCL1 and P32 SDA1 normally CMOS pins function as NMOS only outputs when the bus drive function is selected 18 1 2 Block Diagram Figure 18 1 shows a block diagram of the I2 C bus interface Figure 18 2 shows an example of I O pin connections to external circuits Channel 0 I O pins are NM...

Page 711: ...tor SAR SARX Interrupt generator ICDRS ICDRR ICDRT ICSR ICMR ICCR Internal data bus Interrupt request SCL SDA Legend ICCR ICMR ICSR ICDR SAR SARX PS I2C bus control register I2C bus mode register I2C bus status register I2C bus data register Slave address register Second slave address register X Prescaler Figure 18 1 Block Diagram of I2 C Bus Interface ...

Page 712: ...8 1 3 Input Output Pins Table 18 1 summarizes the input output pins used by the I2 C bus interface Table 18 1 I2 C Bus Interface Pins Channel Name Abbreviation I O Function 0 Serial clock SCL0 I O IIC0 serial clock input output Serial data SDA0 I O IIC0 serial data input output 1 Serial clock SCL1 I O IIC1 serial clock input output Serial data SDA1 I O IIC1 serial data input output Note In the tex...

Page 713: ...3 I2 C bus data register ICDR1 R W H FF86 2 3 I2 C bus mode register ICMR1 R W H 00 H FF87 2 3 Slave address register SAR1 R W H 00 H FF87 2 3 Second slave address register SARX1 R W H 01 H FF86 2 3 Common Serial control register X SCRX R W H 00 H FDB4 DDC switch register DDCSWR R W H 0F H FDB5 Module stop control register B MSTPCRB R W H FF H FDE9 Notes 1 Lower 16 bits of the address 2 The regist...

Page 714: ...RR Bit Initial value R W 7 ICDRR7 R 6 ICDRR6 R 5 ICDRR5 R 4 ICDRR4 R 3 ICDRR3 R 0 ICDRR0 R 2 ICDRR2 R 1 ICDRR1 R ICDRS Bit Initial value R W 7 ICDRS7 6 ICDRS6 5 ICDRR5 4 ICDRS4 3 ICDRS3 0 ICDRS0 2 ICDRS2 1 ICDRS1 ICDRT Bit Initial value R W 7 ICDRT7 W 6 ICDRT6 W 5 ICDRT5 W 4 ICDRT4 W 3 ICDRT3 W 0 ICDRT0 W 2 ICDRT2 W 1 ICDRT1 W TDRE RDRF internal flags Bit Initial value R W RDRF 0 TDRE 0 ...

Page 715: ...rom ICDRT to ICDRS If IIC is in receive mode and no previous data remains in ICDRR the RDRF flag is 0 following transmission reception of one frame of data using ICDRS data is transferred automatically from ICDRS to ICDRR If the number of bits in a frame excluding the acknowledge bit is less than 8 transmit data and receive data are stored differently Transmit data should be written justified towa...

Page 716: ...ditions In transmit mode TRS 1 when a start condition is detected in the bus line state after a start condition is issued in master mode with the I2 C bus format or serial format selected When using formatless mode in transmit mode TRS 1 When data is transferred from ICDRT to ICDRS Data transfer from ICDRT to ICDRS when TRS 1 and TDRE 0 and ICDRS is empty When a switch is made from receive mode TR...

Page 717: ... SAR is assigned to the same address as ICMR and can be written and read only when the ICE bit is cleared to 0 in ICCR SAR is initialized to H 00 by a reset and in hardware standby mode Bits 7 to 1 Slave Address SVA6 to SVA0 Set a unique address in bits SVA6 to SVA0 differing from the addresses of other slave devices connected to the I2 C bus Bit 0 Format Select FS Used together with the FSX bit i...

Page 718: ...W 1 SVAX0 0 R W SARX is an 8 bit readable writable register that stores the second slave address and selects the communication format When the chip is in slave mode and the addressing format is selected if the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition the chip operates as the slave device specified by the master device SARX is assigned to the s...

Page 719: ...d first performs master mode wait control and selects the master mode transfer clock frequency and the transfer bit count ICMR is assigned to the same address as SAR ICMR can be written and read only when the ICE bit is set to 1 in ICCR ICMR is initialized to H 00 by a reset and in hardware standby mode Bit 7 MSB First LSB First Select MLS Selects whether data is transferred MSB first or LSB first...

Page 720: ...low level When the IRIC flag is cleared to 0 in ICCR the wait ends and the acknowledge bit is transferred If WAIT is cleared to 0 data and acknowledge bits are transferred consecutively with no wait inserted The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer regardless of the WAIT setting The setting of this bit is invalid in slave mode Bit 6 WAIT Description 0 Data an...

Page 721: ... 125 kHz 156 kHz 250 kHz 313 kHz 391 kHz 1 0 0 ø 80 62 5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 313 kHz 1 ø 100 50 0 kHz 80 0 kHz 100 kHz 160 kHz 200 kHz 250 kHz 1 0 ø 112 44 6 kHz 71 4 kHz 89 3 kHz 143 kHz 179 kHz 223 kHz 1 ø 128 39 1 kHz 62 5 kHz 78 1 kHz 125 kHz 156 kHz 195 kHz 1 0 0 0 ø 56 89 3 kHz 143 kHz 179 kHz 286 kHz 357 kHz 446 kHz 1 ø 80 62 5 kHz 100 kHz 125 kHz 200 kHz 250 kHz 313 kHz 1 0...

Page 722: ...g the acknowledge bit Bit 2 Bit 1 Bit 0 Bits Frame BC2 BC1 BC0 Synchronous Serial Format I2 C Bus Format 0 0 0 8 9 Initial value 1 1 2 1 0 2 3 1 3 4 1 0 0 4 5 1 5 6 1 0 6 7 1 7 8 18 2 5 I2 C Bus Control Register ICCR Bit Initial value R W Note Only 0 can be written for flag clearing 7 ICE 0 R W 6 IEIC 0 R W 5 MST 0 R W 4 TRS 0 R W 3 ACKE 0 R W 0 SCP 1 W 2 BBSY 0 R W 1 IRIC 0 R W ICCR is an 8 bit r...

Page 723: ...rface Interrupt Enable IEIC Enables or disables interrupts from the I2 C bus interface to the CPU Bit 6 IEIC Description 0 Interrupts disabled Initial value 1 Interrupts enabled Bit 5 Master Slave Select MST Bit 4 Transmit Receive Select TRS MST selects whether the I2 C bus interface operates in master mode or slave mode TRS selects whether the I2 C bus interface operates in transmit mode or recei...

Page 724: ...MST 0 in case of clearing condition 2 Bit 4 TRS Description 0 Receive mode Clearing conditions 1 When 0 is written by software in cases other than setting condition 3 2 When 0 is written in TRS after reading TRS 1 in case of clearing condition 3 3 When bus arbitration is lost after transmission is started in I2 C bus format master mode 4 When the SW bit in DDCSWR changes from 1 to 0 Initial value ...

Page 725: ...continuous data transfer but if data transmission is completed with a 1 acknowledge bit when the ACKE bit is set to 1 the DTC is not activated and an interrupt is generated if enabled Depending on the receiving device the acknowledge bit may be significant in indicating completion of processing of the received data for instance or may be fixed at 1 and have no significance Bit 3 ACKE Description 0...

Page 726: ...eral call address is detected in slave receive mode when bus arbitration is lost in master transmit mode and when a stop condition is detected IRIC is set at different times depending on the FS bit in SAR and the WAIT bit in ICMR See section 18 3 6 IRIC Setting Timing and SCL Control The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR IRIC is cleared...

Page 727: ...rbitration is lost when the AL flag is set to 1 5 When 1 is received as the acknowledge bit when the ACKE bit is 1 when the ACKB bit is set to 1 I2 C bus format slave mode 1 When the slave address SVA SVAX matches when the AAS and AASX flags are set to 1 and at the end of data transfer up to the subsequent retransmission start condition or stop condition detection when the TDRE or RDRF flag is set...

Page 728: ...transfer using the DTC The TDRE or RDRF flag is cleared however since the specified number of ICDR reads or writes have been completed Table 18 3 shows the relationship between the flags and the transfer states Table 18 3 Flags and Transfer States MST TRS BBSY ESTP STOP IRTR AASX AL AAS ADZ ACKB State 1 0 1 0 0 0 0 0 0 0 0 0 0 Idle state flag clearing required 1 1 0 0 0 0 0 0 0 0 0 Start condition...

Page 729: ...tion with the BBSY flag 1 Reading always returns a value of 1 Writing is ignored Initial value 18 2 6 I2 C Bus Status Register ICSR Bit Initial value R W Note Only 0 can be written for flag clearing 7 ESTP 0 R W 6 STOP 0 R W 5 IRTR 0 R W 4 AASX 0 R W 3 AL 0 R W 0 ACKB 0 R W 2 AAS 0 R W 1 ADZ 0 R W ICSR is an 8 bit readable writable register that performs flag confirmation and acknowledge confirmat...

Page 730: ...e IRIC flag is cleared to 0 Initial value 1 In I2 C bus format slave mode Normal stop condition detected Setting condition When a stop condition is detected after completion of frame transfer In other modes No meaning Bit 5 I2 C Bus Interface Continuous Transmission Reception Interrupt Request Flag IRTR Indicates that the I2 C bus interface has issued an interrupt request to the CPU and the source...

Page 731: ...ASX after it has been set to 1 then writing 0 in AASX AASX is also cleared automatically when a start condition is detected Bit 4 AASX Description 0 Second slave address not recognized Clearing conditions 1 When 0 is written in AASX after reading AASX 1 2 When a start condition is detected 3 In master mode Initial value 1 Second slave address recognized Setting condition When the second slave addr...

Page 732: ...s Recognition Flag AAS In I2 C bus format slave receive mode this flag is set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR or if the general call address H 00 is detected AAS is cleared by reading AAS after it has been set to 1 then writing 0 in AAS In addition AAS is reset automatically by write access to ICDR in transmit mode or read access to ICDR in rece...

Page 733: ...ral call address is detected in slave receive mode and FSX 0 or FS 0 Bit 0 Acknowledge Bit ACKB Stores acknowledge data In transmit mode after the receiving device receives data it returns acknowledge data and this data is loaded into ACKB In receive mode after data has been received the acknowledge data set in this bit is sent to the transmitting device When this bit is read in transmission when ...

Page 734: ...S0 in ICMR of IIC1 selects the transfer rate in master mode For details see section 18 2 4 I2 C Bus Mode Register ICMR Bit 5 I2 C Transfer Select 0 IICX0 This bit together with bits CKS2 to CKS0 in ICMR of IIC0 selects the transfer rate in master mode For details see section 18 2 4 I2 C Bus Mode Register ICMR Bit 4 I2 C Master Enable IICE Controls CPU access to the I2 C bus interface data and cont...

Page 735: ... to if read they will always return a value of 1 When a write operation is performed on these bits a clear signal is generated for the internal latch circuit of the corresponding module s and the internal state of the IIC module s is initialized The write data for these bits is not retained To perform IIC clearance bits CLR3 to CLR0 must be written to simultaneously using an MOV instruction Do not...

Page 736: ...ansition is made to module stop mode For details see section 24 5 Module Stop Mode MSTPCRB is initialized to H FF by a power on reset and in hardware standby mode It is not initialized by a manual reset and in software standby mode Bit 4 Module Stop MSTPB4 Specifies IIC channel 0 module stop mode Bit 4 MSTPB4 Description 0 IIC channel 0 module stop mode is cleared 1 IIC channel 0 module stop mode ...

Page 737: ...re 18 4 Figure 18 5 shows the I2 C bus timing The symbols used in figures 18 3 to 18 5 are explained in table 18 4 S SLA R W A DATA A A A P 1 1 1 1 n 7 1 m a I2C bus format FS 0 or FSX 0 b I2C bus format start condition retransmission FS 0 or FSX 0 n transfer bit count n 1 to 8 m transfer frame count m 1 S SLA R W A DATA 1 1 1 n1 7 1 m1 S SLA R W A DATA A A P 1 1 1 n2 7 1 m2 1 1 1 A A n1 and n2 tr...

Page 738: ...rns an acknowledge signal The transmission procedure and operations are described below 1 Set the ICE bit in ICCR to 1 Set bits MLS WAIT and CKS2 to CKS0 in ICMR and bit IICX in STCR according to the operating mode 2 Read the BBSY flag in ICCR to confirm that the bus is free then set bits MST and TRS to 1 in ICCR to select master transmit mode Next write 1 to BBSY and 0 to SCP This changes SDA fro...

Page 739: ...performed in synchronization with the internal clock Data can be transmitted sequentially by repeating steps 4 and 5 To end transmission after clearing the IRIC flag and transmitting the final data with no more transmit data in ICDRT write H FF dummy data to ICDR and then write 0 to BBSY and SCP in ICCR when the IRIC flag is set again This changes SDA from low to high when SCL is high and generate...

Page 740: ...ave output 2 1 2 3 1 4 3 6 5 8 7 9 Bit 7 Bit 6 Bit 5 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRIC ICDRT ICDRS TDRE SCL master output Interrupt request generation Data 2 Data 1 6 ICDR write ICDR write 6 ICDR write 6 IRIC clearance 6 IRIC clearance User processing Data 1 Data 1 Data 2 Data 3 Data 2 7 7 A Figure 18 7 Example of Master Transmit Mode Continuous Transmit Operation Timing MLS WAI...

Page 741: ...receive operation continues If reception of the next frame ends before the ICDR read IRIC flag clearing in 4 is performed SCL is automatically fixed low in synchronization with the internal clock 4 Read ICDR and clear the IRIC flag in ICCR to 0 The RDRF flag is cleared to 0 Data can be received continuously by repeating steps 3 and 4 As the RDRF internal flag is cleared to 0 when reception is star...

Page 742: ...ve receive mode are described below 1 Set the ICE bit in ICCR to 1 Set the MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode 2 When the start condition output by the master device is detected the BBSY flag in ICCR is set to 1 3 When the slave address matches in the first frame following the start condition the device operates as the slave device specified by the mast...

Page 743: ...low to high when SCL is high and the stop condition is detected the BBSY flag in ICCR is cleared to 0 SDA master output SDA slave output 2 1 2 1 4 3 6 5 8 7 9 Bit 7 Bit 6 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRIC ICDRS ICDRR RDRF SCL master output Start condition issuance SCL slave output Interrupt request generation Address R W Address R W 5 ICDR read 5 IRIC clearance User processing S...

Page 744: ... MLS bit in ICMR and the MST and TRS bits in ICCR according to the operating mode 2 When the slave address matches in the first frame following detection of the start condition the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal At the same time the IRIC flag in ICCR is set to 1 If the IEIC bit in ICCR has been set to 1 an interrupt request is sent to the CPU I...

Page 745: ...internal flag and the IRIC and IRTR flags are set to 1 again 5 To continue transmission clear the IRIC flag to 0 then write the next data to be transmitted into ICDR The TDRE flag is cleared to 0 Transmit operations can be performed continuously by repeating steps 4 and 5 To end transmission write H FF to ICDR to release SDA on the slave side When SDA is changed from low to high when SCL is high a...

Page 746: ...2 shows the IRIC set timing and SCL control a When WAIT 0 and FS 0 or FSX 0 I2C bus format no wait SCL SDA IRIC User processing Clear IRIC Write to ICDR transmit or read ICDR receive 1 A 8 1 1 A 7 1 8 9 7 b When WAIT 1 and FS 0 or FSX 0 I2C bus format wait inserted SCL SDA IRIC User processing Clear IRIC Clear IRIC Write to ICDR transmit or read ICDR receive SCL SDA IRIC User processing c When FS ...

Page 747: ...TC ICDR write Transmission by CPU ICDR write Reception by CPU ICDR read Reception by CPU ICDR read Dummy data read Processing by CPU ICDR read Actual data transmission reception Transmission by DTC ICDR write Reception by DTC ICDR read Transmission by DTC ICDR write Reception by DTC ICDR read Dummy data H FF write Processing by DTC ICDR write Last frame processing Not necessary Reception by CPU IC...

Page 748: ...SDA input signal is sampled on the system clock but is not passed forward to the next circuit unless the outputs of both latches agree If they do not agree the previous value is held System clock period Sampling clock C D Q Latch C D Q Latch SCL or SDA input signal Match detector Internal SCL or SDA signal Sampling clock Figure 18 13 Block Diagram of Noise Canceler 18 3 9 Sample Flowcharts Figures...

Page 749: ...R End of transmission ACKB 1 No Yes Write BBSY 0 and SCP 0 in ICSR End Master receive mode No IRIC 1 Yes 1 Test the status of the SCL and SDA lines 2 Select master transmit mode 3 Generate a start condition 4 Set transmit data for the first byte slave address R W 5 Wait for 1 byte to be transmitted 6 Test for acknowledgement by the designated slave device 7 Set transmit data for the second and sub...

Page 750: ...0 in ICCR End 1 2 3 4 5 6 7 8 9 10 Yes No 1 Select receive mode 2 Set acknowledge data 3 Start receiving The first read is a dummy read 4 Wait for 1 byte to be received 5 Set acknowledge data for the last receive 6 Start the last receive 7 Wait for 1 byte to be received 8 Select transmit mode 9 Read the last receive data if ICDR is read without selecting transmit mode receive operations will resum...

Page 751: ...et ACKB 0 in ICSR Read ICDR Read IRIC in ICCR Read ICDR IRIC 1 Clear IRIC in ICCR End General call address processing Description omitted Slave transmit mode 1 Select slave receive mode 2 Wait for the first byte to be received slave address 3 Start receiving The first read is a dummy read 4 Wait for the transfer to end 5 Set acknowledge data for the last receive 6 Start the last receive 7 Wait for...

Page 752: ...e transmitted 3 Test for end of transfer 4 Select slave receive mode 5 Dummy read to release the SCL line Figure 18 17 Flowchart for Slave Receive Mode Example 18 3 10 Initialization of Internal State The IIC has a function for forcible initialization of its internal state if a deadlock occurs during communication Initialization is executed by 1 setting bits CLR3 to CLR0 in the DDCSWR register or ...

Page 753: ...R3 to CLR0 must be written to simultaneously using an MOV instruction Do not use a bit manipulation instruction such as BCLR Similarly when clearing is required again all the bits must be written to simultaneously in accordance with the setting If a flag clearing setting is made during transmission reception the IIC module will stop transmitting receiving at that point and the SCL and SDA pins wil...

Page 754: ... including automatic transfer from ICDRT to ICDRS Read access to ICDR when ICE 1 and TRS 0 including automatic transfer from ICDRS to ICDRR Table 18 6 shows the timing of SCL and SDA output in synchronization with the internal clock Timings on the bus are determined by the rise and fall times of signals affected by the bus load capacitance series resistance and parallel resistance Table 18 6 I2 C ...

Page 755: ...z ø 20 MHz ø 25 MHz 0 7 5tcyc Standard mode 1000 ns 1000 ns 937 ns 750 ns 468 ns 375 ns 300 ns High speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 1 17 5tcyc Standard mode 1000 ns 1000 ns 1000 ns 1000 ns 1000 ns 875 ns 700 ns High speed mode 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns 300 ns The I2 C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns ...

Page 756: ...se and fall times by means of a pull up resistor and capacitive load b reducing the transfer rate to meet the specifications or c selecting devices whose input timing permits this output timing for use as slave devices connected to the I2 C bus ...

Page 757: ... 1 3900 1 3938 1 3950 1 3960 1 tSr High speed mode 300 1300 750 1 825 1 850 1 888 1 900 1 910 1 tSTAHO 0 5tSCLO 1tcyc Standard mode 250 4000 4550 4625 4650 4688 4700 4710 tSf High speed mode 250 600 800 875 900 938 950 960 tSTASO 1tSCLO tSr Standard mode 1000 4700 9000 9000 9000 9000 9000 9000 High speed mode 300 600 2200 2200 2200 2200 2200 2200 tSTOSO 0 5tSCLO 2tcyc Standard mode 1000 4000 4400 ...

Page 758: ...operation in master receive mode set the TRS bit to 1 and write 0 to BBSY and SCP in ICCR This changes SDA from low to high when SCL is high and generates the stop condition After this receive data can be read by means of an ICDR read but if data remains in the buffer the ICDRS receive data will not be transferred to ICDR and so it will not be possible to read the second byte of data If it is nece...

Page 759: ... and SCP Confirmation of stop condition generation 0 read from BBSY Start condition issuance Figure 18 18 Points for Attention Concerning Reading of Master Receive Data Notes on Start Condition Issuance for Retransmission Figure 18 19 shows the timing of start condition issuance for retransmission and the timing for subsequently writing data to ICDR together with the corresponding flowchart ...

Page 760: ...ther SCL is low 3 Issue restart condition instruction for retransmission 4 Determine whether SCL is high 5 Set transmit data slave address R W Other processing Yes Yes Read SCL pin SCL High No Yes Start condition retransmission SCL bit7 ACK IRIC 1 IRIC determination Determination of SCL low 2 3 Start condition instruction issuance 4 Determination of SCL high 5 ICDR write SDA Figure 18 19 Flowchart...

Page 761: ...re is a slave device of the type that drives SCL low to effect a wait issue the stop condition instruction after reading SCL and determining it to be low as shown below Stop condition SCL IRIC 1 Determination of SCL low 9th clock VIH High period secured 2 Stop condition instruction issuance SDA As waveform rise is late SCL is detected as low Figure 18 20 Timing of Stop Condition Issuance ...

Page 762: ...e 10 64 µs per channel at 25 MHz operation Choice of single mode or scan mode Single mode Single channel A D conversion Scan mode Continuous A D conversion on 1 to 4 channels Four data registers Conversion results are held in a 16 bit data register for each channel Sample and hold function Three kinds of conversion start Choice of software or timer conversion start trigger TPU or 8 bit timer or AD...

Page 763: ...C R A D D R D A D D R C A D D R B A D D R A AVCC Vref AVSS AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 ADTRG Conversion start trigger from 8 bit timer or TPU Successive approximations register Multiplexer ADCR ADCSR ADDRA ADDRB ADDRC ADDRD A D control register A D control status register A D data register A A D data register B A D data register C A D data register D Figur...

Page 764: ... Analog block power supply Analog ground pin AVSS Input Analog block ground and reference voltage Reference voltage pin Vref Input A D conversion reference voltage Analog input pin 0 AN0 Input Channel set 0 CH3 0 group 0 analog inputs Analog input pin 1 AN1 Input Analog input pin 2 AN2 Input Analog input pin 3 AN3 Input Analog input pin 4 AN4 Input Channel set 0 CH3 0 group 1 analog inputs Analog ...

Page 765: ...r BH ADDRBH R H 00 H FF92 A D data register BL ADDRBL R H 00 H FF93 A D data register CH ADDRCH R H 00 H FF94 A D data register CL ADDRCL R H 00 H FF95 A D data register DH ADDRDH R H 00 H FF96 A D data register DL ADDRDL R H 00 H FF97 A D control status register ADCSR R W 2 H 00 H FF98 A D control register ADCR R W H 33 H FF99 Module stop control register A MSTPCRA R W H 3F H FDE8 Notes 1 Lower 1...

Page 766: ...the lower 2 bits are transferred to the lower byte bits 7 and 6 and stored Bits 5 to 0 are always read as 0 The correspondence between the analog input channels and ADDR registers is shown in table 19 3 ADDR can always be read by the CPU The upper byte can be read directly but for the lower byte data transfer is performed via a temporary register TEMP For details see section 19 3 Interface to Bus ...

Page 767: ...lag ADF Status flag that indicates the end of A D conversion Bit 7 ADF Description 0 Clearing conditions Initial value When 0 is written to the ADF flag after reading ADF 1 When the DTC is activated by an ADI interrupt and ADDR is read 1 Setting conditions Single mode When A D conversion ends Scan mode When A D conversion ends on all specified channels Bit 6 A D Interrupt Enable ADIE Selects enabl...

Page 768: ...d to 0 by software a reset or a transition to standby mode or module stop mode Bit 4 Scan Mode SCAN Selects single mode or scan mode as the A D conversion operating mode See section 19 4 Operation for single mode and scan mode operation Only set the SCAN bit while conversion is stopped ADST 0 Bit 4 SCAN Description 0 Single mode Initial value 1 Scan mode Bit 3 Channel Select 3 CH3 Switches the ana...

Page 769: ...ADST 0 Channel Selection Description CH3 CH2 CH1 CH0 Single Mode SCAN 0 Scan Mode SCAN 1 0 0 0 0 AN0 Initial value AN0 1 AN1 AN0 AN1 1 0 AN2 AN0 to AN2 1 AN3 AN0 to AN3 1 0 0 AN4 AN4 1 AN5 AN4 AN5 1 0 AN6 AN4 to AN6 1 AN7 AN4 to AN7 1 0 0 0 AN8 AN8 1 AN9 AN8 AN9 1 0 AN10 AN8 to AN10 1 AN11 AN8 to AN11 1 0 0 AN12 AN12 1 AN13 AN12 AN13 1 0 AN14 AN12 to AN14 1 AN15 AN12 to AN15 ...

Page 770: ...ption 0 0 A D conversion start by software is enabled Initial value 1 A D conversion start by TPU conversion start trigger is enabled 1 0 A D conversion start by 8 bit timer conversion start trigger is enabled 1 A D conversion start by external trigger pin ADTRG is enabled Bits 5 4 1 and 0 Reserved They are always read as 1 and cannot be modified Bits 3 and 2 Clock Select 1 and 0 CKS1 CKS0 These b...

Page 771: ...verter operation stops at the end of the bus cycle and a transition is made to module stop mode Registers cannot be read or written to in module stop mode For details see section 24 5 Module Stop Mode MSTPCRA is initialized to H 3F by a reset and in hardware standby mode It is not initialized by a manual reset and in software standby mode Bit 1 Module Stop MSTPA1 Specifies the A D converter module...

Page 772: ...yte value is transferred to TEMP Next when the lower byte is read the TEMP contents are transferred to the CPU When reading ADDR always read the upper byte before the lower byte It is possible to read only the upper byte but if only the lower byte is read incorrect data may be obtained Figure 19 2 shows the data flow for ADDR access Bus master H AA ADDRnH H AA ADDRnL H 40 Lower byte read ADDRnH H ...

Page 773: ...t A D conversion After making the necessary changes set the ADST bit to 1 to start A D conversion again The ADST bit can be set at the same time as the operating mode or input channel is changed Typical operations when channel 1 AN1 is selected in single mode are described next Figure 19 3 shows a timing diagram for this example 1 Single mode is selected SCAN 0 input channel AN1 is selected CH3 0 ...

Page 774: ...ate of channel 3 AN3 Note Vertical arrows indicate instructions executed by software Set Set Clear Clear A D conversion result 1 A D conversion A D conversion result 2 Read conversion result Read conversion result Idle Idle Idle Idle Idle Idle A D conversion Set Figure 19 3 Example of A D Converter Operation Single Mode Channel 1 Selected ...

Page 775: ... be set at the same time as the operating mode or input channel is changed Typical operations when three channels AN0 to AN2 are selected in scan mode are described next Figure 19 4 shows a timing diagram for this example 1 Scan mode is selected SCAN 1 channel set 0 is selected CH3 0 scan group 0 is selected CH2 0 analog input channels AN0 to AN2 are selected CH1 1 CH0 0 and A D conversion is star...

Page 776: ...a currently being converted is ignored Clear 1 Idle Idle A D conversion time Idle Continuous A D conversion execution A D conversion 1 Idle Idle Idle Idle Idle Transfer 2 A D conversion 3 A D conversion 2 A D conversion 5 A D conversion 4 A D conversion result 1 A D conversion result 2 A D conversion result 3 A D conversion result 4 Figure 19 4 Example of A D Converter Operation Scan Mode 3 Channe...

Page 777: ...iming of the write access to ADCSR The total conversion time therefore varies within the ranges indicated in table 19 4 In scan mode the values given in table 19 4 apply to the first conversion time The values given in table 19 5 apply to the second and subsequent conversions In both cases set bits CKS1 and CKS0 in ADCR to give a conversion time of at least 10 µs when AVCC 4 5 V and at least 16 µs...

Page 778: ...CKS1 CKS0 Conversion Time State 0 0 512 Fixed 1 256 Fixed 1 0 128 Fixed 1 64 Fixed 19 4 4 External Trigger Input Timing A D conversion can be externally triggered When the TRGS1 and TRGS0 bits are set to 11 in ADCR external trigger input is enabled at the ADTRG pin A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR starting A D conversion Other operations in both single and scan modes...

Page 779: ... Other Pins 1 Analog input voltage range The voltage applied to analog input pin ANn during A D conversion should be in the range AVSS ANn Vref 2 Relation between AVCC AVSS and VCC VSS As the relationship between AVCC AVSS and VCC VSS set AVSS VSS If the A D converter is not used the AVCC and AVSS pins must on no account be left open 3 Vref input range The analog reference voltage input at the Vre...

Page 780: ...ected to AVCC and Vref and the filter capacitor connected to AN0 to AN15 must be connected to AVSS If a filter capacitor is connected as shown in figure 19 7 the input currents at the analog input pins AN0 to AN15 are averaged and so an error may arise Also when A D conversion is performed frequently as in scan mode if the current charged and discharged by the capacitance of the sample and hold ci...

Page 781: ... the minimum voltage value B 0000000000 H 00 to B 0000000001 H 01 see figure 19 10 Full scale error The deviation of the analog input voltage value from the ideal A D conversion characteristic when the digital output changes from B 1111111110 H 3E to B 1111111111 H 3F see figure 19 10 Quantization error The deviation inherent in the A D converter given by 1 2 LSB see figure 19 9 Nonlinearity error...

Page 782: ...1 110 101 100 011 010 001 000 FS Quantization error Digital output Ideal A D conversion characteristic Analog input voltage 1 1024 2 1024 1022 1024 1023 1024 Figure 19 9 A D Conversion Precision Definitions 1 ...

Page 783: ...r s sample and hold circuit input capacitance to be charged within the sampling time if the sensor output impedance exceeds 10 kΩ charging may be insufficient and it may not be possible to guarantee the A D conversion precision However if a large capacitance is provided externally the input load will essentially comprise only the internal input resistance of 10 kΩ and the signal source impedance i...

Page 784: ...nection to an electrically stable GND such as AVSS Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board so acting as antennas A D converter equivalent circuit H8S 2633 Series 20 pF Cin 15 pF 10 kΩ to 5 kΩ Low pass filter C to 0 1 µF Sensor output impedance Sensor input Figure 19 11 Example of Analog Input Circuit ...

Page 785: ... resolution Four channel output Maximum conversion time 10 µs with 20 pF load capacitance Output voltage 0 V to Vref D A output retention in software standby mode Possible to set module stop mode Operation of D A converter is disenabled by initial values It is possible to access the register by canceling module stop mode 20 1 2 Block Diagram Figure 20 1 shows a block diagram of the D A converter ...

Page 786: ...ata bus Internal data bus 8 bit D A DADR0 DADR2 DADR1 DADR3 DACR Control circuit Legend DACR DADR0 to DADR3 D A control register D A data register 0 to 3 Vref AVCC DA1 DA3 DA0 DA2 AVSS Figure 20 1 Block Diagram of D A Converter ...

Page 787: ...tput 3 DA3 Output Analog output channel 3 Reference voltage Vref Input Reference voltage of analog section 20 1 4 Register Configuration Table 20 2 lists the registers of the D A converter module Table 20 2 D A Converter Registers Channel Name Abbreviation R W Initial Value Address 0 1 D A data register 0 DADR0 R W H 00 H FFA4 D A data register 1 DADR1 R W H 00 H FFA5 D A control register 01 DACR0...

Page 788: ...ers are initialized to H 00 by a reset and in hardware standby mode 20 2 2 D A Control Register 01 and 23 DACR01 and DACR23 7 DAOE1 0 R W 6 DAOE0 0 R W 5 DAE 0 R W 4 1 3 1 0 1 2 1 1 1 Bit Initial value R W DACR01 and DACR23 are an 8 bit readable writable register that controls the operation of the D A converter module DACR01 and DACR23 are initialized to H 1F by a reset and in hardware standby mod...

Page 789: ...onversion 0 0 Disabled on channels 0 and 1 channels 2 and 3 1 0 Enabled on channel 0 channel 2 Disabled on channel 1 channel 3 1 Enabled on channels 0 and 1 channels 2 and 3 1 0 0 Disabled on channel 0 channel 2 Enabled on channel 1 channel 3 1 Enabled on channels 0 and 1 channels 2 and 3 1 Enabled on channels 0 and 1 channels 2 and 3 Don t care If the H8S 2633 Series chip enters software standby ...

Page 790: ... W MSTPCRC MSTPCRA and MSTPCRC are an 8 bit readable writable registers that performs module stop mode control When the MSTPA2 and MSTPC5 are set to 1 the D A converter halts and enters module stop mode at the end of the bus cycle Register read write is disenabled in module stop mode See section 24 5 Module Stop Mode for details MSTPCRA is initialized to H 3F by a power on reset and in hardware st...

Page 791: ...d 1 module stop mode is cleared 1 D A converter channels 0 and 1 module stop mode is set Initial value Module Stop Control Register C MSTPCRC Bit 5 Module Stop MSTPC5 Specifies D A converter channels 2 and 3 module stop mode Bit 5 MSTPC5 Description 0 D A converter channels 2 and 3 module stop mode is cleared 1 D A converter channels 2 and 3 module stop mode is set Initial value ...

Page 792: ...begins when the DAOE0 bit in DACR is set to 1 After the elapse of the conversion time analog output appears at the DA0 pin The output value is Vref DADR0 value 256 This output continues until a new value is written in DADR0 or the DAOE0 bit is cleared to 0 If a new value is written in DADR0 conversion begins immediately Output of the converted result begins after the conversion time When the DAOE0...

Page 793: ...ata This makes it possible to perform fast word data transfer The on chip RAM can be enabled or disabled by means of the RAM enable bit RAME in the system control register SYSCR 21 1 1 Block Diagram Figure 21 1 shows a block diagram of the on chip RAM Internal data bus upper 8 bits Internal data bus lower 8 bits H FFB000 H FFB002 H FFB004 H FFFFC0 H FFB001 H FFB003 H FFB005 H FFFFC1 H FFFFFE H FFF...

Page 794: ...5 INTM1 0 R W 4 INTM0 0 R W 3 NMIEG 0 R W 0 RAME 1 R W 2 MRESE 0 R W 1 0 Bit Initial value R W The on chip RAM is enabled or disabled by the RAME bit in SYSCR For details of other bits in SYSCR see section 3 2 2 System Control Register SYSCR Bit 0 RAM Enable RAME Enables or disables the on chip RAM The RAME bit is initialized when the reset state is released It is not initialized in software stand...

Page 795: ...an internal 16 bit data bus it can be written to and read in byte or word units Each type of access can be performed in one state Even addresses use the upper 8 bits and odd addresses use the lower 8 bits Word data must start at an even address 21 4 Usage Notes When Using the DTC DTC register information can be located in addresses H FFEBC0 to H FFEFBF When the DTC is used the RAME bit must not be...

Page 796: ...er byte and the erase time is 100 ms typ Reprogramming capability The flash memory can be reprogrammed up to 100 times On board programming modes There are two modes in which flash memory can be programmed erased verified on board Boot mode User program mode Automatic bit rate adjustment With data transfer in boot mode the LSI s bit rate can be automatically adjusted to match the transfer bit rate...

Page 797: ...ess bus Internal data bus 16 bits FWE pin Mode pin EBR1 EBR2 RAMER FLPWCR FLMCR1 Flash memory control register 1 Flash memory control register 2 Erase block register 1 Erase block register 2 RAM emulation register Flash memory power control register Legend FLMCR1 FLMCR2 EBR1 EBR2 RAMER FLPWCR Figure 22 1 Block Diagram of Flash Memory ...

Page 798: ...modes are provided as modes to write and erase the flash memory Boot mode On board programming mode User program mode User mode on chip ROM enabled Reset state Programmer mode RES 0 FWE 1 FWE 0 1 1 2 Notes Only make a transition between user mode and user program mode when the CPU is not accessing the flash memory 1 RAM emulation possible 2 MD0 0 MD1 0 MD2 0 P14 0 P16 0 PF0 1 RES 0 MD1 0 MD2 0 FWE...

Page 799: ...hand in the host 2 Programming control program transfer When boot mode is entered the boot program in the H8S 2633 originally incorporated in the chip is started and the programming control program in the host is transferred to RAM via SCI communication The boot program required for flash memory erasing is automatically transferred to the RAM boot program area 3 Flash memory initialization The era...

Page 800: ...ogramming erase control program should be prepared in the host or in the flash memory 2 Programming erase control program transfer When user program mode is entered user software confirms this fact executes transfer program in the flash memory and transfers the programming erase control program to RAM 3 Flash memory initialization The programming erase program in RAM is executed and the flash memo...

Page 801: ...ory Emulation block RAM SCI Overlap RAM emulation is performed on data written in RAM Figure 22 3 Reading Overlap RAM Data in User Mode or User Program Mode When overlap RAM data is confirmed the RAMS bit is cleared RAM overlap is released and writes should actually be performed to the flash memory When the programming control program is transferred to RAM ensure that the transfer destination and ...

Page 802: ...Program Mode 22 2 5 Differences between Boot Mode and User Program Mode Table 22 1 Differences between Boot Mode and User Program Mode Boot Mode User Program Mode Total erase Yes Yes Block erase No Yes Programming control program Program program verify Erase erase verify Program program verify Emulation Note To be provided by the user in accordance with the recommended algorithm ...

Page 803: ...le 22 2 Pin Configuration Pin Name Abbreviation I O Function Reset RES Input Reset Flash write enable FWE Input Flash memory program erase protection by hardware Mode 2 MD2 Input Sets MCU operating mode Mode 1 MD1 Input Sets MCU operating mode Mode 0 MD0 Input Sets MCU operating mode Port F0 PF0 Input Sets MCU operating mode in programmer mode Port 16 P16 Input Sets MCU operating mode in programme...

Page 804: ...t to 1 3 When a high level is input to the FWE pin the initial value is H 80 4 When a low level is input to the FWE pin or if a high level is input and the SWE1 bit in FLMCR1 is not set these registers are initialized to H 00 5 FLMCR1 FLMCR2 EBR1 and EBR2 RAMER and FLPWCR are 8 bit registers Use byte access on these registers 22 5 Register Descriptions 22 5 1 Flash Memory Control Register 1 FLMCR1...

Page 805: ...ription 0 When a low level is input to the FWE pin hardware protected state 1 When a high level is input to the FWE pin Bit 6 Software Write Enable Bit 1 SWE1 This bit selects write and erase valid invalid of the flash memory Set it when setting bits 5 to 0 bits 7 to 0 of EBR1 and bits 3 to 0 of EBR2 Bit 6 SWE1 Description 0 Writes disabled Initial value 1 Writes enabled Setting condition When FWE...

Page 806: ...t the SWE1 ESU1 PSU1 PV1 E1 or P1 bit at the same time Bit 3 EV1 Description 0 Erase verify mode cleared Initial value 1 Transition to erase verify mode Setting condition When FWE 1 and SWE1 1 Bit 2 Program Verify 1 PV1 Selects program verify mode transition or clearing Do not set the SWE1 ESU1 PSU1 EV1 E1 or P1 bit at the same time Bit 2 PV1 Description 0 Program verify mode cleared Initial value...

Page 807: ...ed Initial value 1 Transition to program mode Setting condition When FWE 1 SWE1 1 and PSU1 1 22 5 2 Flash Memory Control Register 2 FLMCR2 FLMCR2 is an 8 bit register used for flash memory operating mode control FLMCR2 is initialized to H 00 by a power on reset and in hardware standby mode and software standby mode When on chip flash memory is disabled a read will return H 00 Bit 7 6 5 4 3 2 1 0 F...

Page 808: ...R1 EBR1 is an 8 bit register that specifies the flash memory erase area block by block EBR1 is initialized to H 00 by a power on reset in hardware standby mode and software standby mode when a low level is input to the FWE pin and when a high level is input to the FWE pin and the SWE1 bit in FLMCR1 is not set When a bit in EBR1 is set to 1 the corresponding block can be erased Other blocks are era...

Page 809: ...oth EBR1 and EBR2 to be automatically cleared to 0 Bits 7 to 4 are reserved and must only be written with 0 When on chip flash memory is disabled a read will return H 00 and writes are invalid The flash memory erase block configuration is shown in table 22 4 Bit 7 6 5 4 3 2 1 0 EB11 EB10 EB9 EB8 Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W Table 22 4 Flash Memory Erase Blocks ...

Page 810: ...uld not be accessed immediately after this register has been modified Normal execution of an access immediately after register modification is not guaranteed Bit 7 6 5 4 3 2 1 0 RAMS RAM2 RAM1 RAM0 Initial value 0 0 0 0 0 0 0 0 R W R R R W R W R W R W R W R W Bits 7 and 6 Reserved These bits always read 0 Bits 5 and 4 Reserved Only 0 may be written to these bits Bit 3 RAM Select RAMS Specifies sel...

Page 811: ...dresses Block Name RAMS RAM1 RAM1 RAM0 H FFD000 H FFDFFF RAM area 4 kbytes 0 H 000000 H 000FFF EB0 4 kbytes 1 0 0 0 H 001000 H 001FFF EB1 4 kbytes 1 0 0 1 H 002000 H 002FFF EB2 4 kbytes 1 0 1 0 H 003000 H 003FFF EB3 4 kbytes 1 0 1 1 H 004000 H 004FFF EB4 4 kbytes 1 1 0 0 H 005000 H 005FFF EB5 4 kbytes 1 1 0 1 H 006000 H 006FFF EB6 4 kbytes 1 1 1 0 H 007000 H 007FFF EB7 4 kbytes 1 1 1 1 Don t care ...

Page 812: ...5 7 Serial Control Register X SCRX Bit 7 6 5 4 3 2 1 0 IICX1 IICX0 IICE FLSHE Initial value 0 0 0 0 0 0 0 0 R W R W R W R W R W R W R W R W R W SCRX is an 8 bit readable writable register that controls on chip flash memory SCRX is initialized to H 00 by a reset and in hardware standby mode Bit 7 Reserved This bit should always be written with 0 Bits 6 and 5 I2 C Transfer Rate Select IICX1 IICX0 Th...

Page 813: ...ngs for transition to each of these modes are shown in table 22 6 For a diagram of the transitions to the various flash memory modes see figure 22 2 Table 22 6 Setting On Board Programming Modes Mode FWE MD2 MD1 MD0 Boot mode Expanded mode 1 0 1 0 Single chip mode 0 1 1 User program mode Expanded mode 1 1 1 0 Single chip mode 1 1 1 22 6 1 Boot Mode When boot mode is used the flash memory programmi...

Page 814: ...ogramming algorithm given later The system configuration in boot mode is shown in figure 22 6 and the boot mode execution procedure in figure 22 7 RxD2 TxD2 SCI2 H8S 2633 Series Flash memory Write data reception Verify data transmission Host On chip RAM Figure 22 6 System Configuration in Boot Mode ...

Page 815: ...mits one H 55 data byte After receiving H 55 LSI transmits one H AA data byte to host Host transmits number of programming control program bytes N upper byte followed by lower byte H8S 2633 transmits received number of bytes to host as verify data echo back n 1 Host transmits programming control program sequentially in byte units H8S 2633 transmits received programming control program to host as v...

Page 816: ... H8S 2633 Series If reception cannot be performed normally initiate boot mode again reset and repeat the above operations Depending on the host s transmission bit rate and the H8S 2633 Series system clock frequency there will be a discrepancy between the bit rates of the host and the H8S 2633 Series Set the host transfer bit rate at 2 400 4 800 9 600 or 19 200 bps to operate the SCI properly Table...

Page 817: ...s out of reset in boot mode it measures the low level period of the input at the SCI s RxD2 pin The reset should end with RxD2 high After the reset ends it takes approximately 100 states before the chip is ready to measure the low level period of the RxD2 pin In boot mode if any data has been programmed into the flash memory if all data is not 1 all flash memory blocks are erased Boot mode is for ...

Page 818: ...pins from becoming output signal pins during a reset or to prevent collision with signals outside the microcomputer Notes 1 Mode pin and FWE pin input must satisfy the mode programming setup time tMDS 4 states with respect to the reset release timing 2 For further information on FWE application and disconnection see section 22 13 Flash Memory Programming and Erasing Precautions 3 See appendix D Pi...

Page 819: ...FWE assessment program and transfer program and the program erase control program if necessary beforehand Note Do not apply a constant high level to the FWE pin Apply a high level to the FWE pin only when the flash memory is programmed or erased Also while a high level is applied to the FWE pin the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway ...

Page 820: ... memory If the program is to be located in external memory the instruction for writing to flash memory and the following instruction should be placed in on chip RAM Also ensure that the DTC and DMAC is not activated before or after execution of the flash memory write instruction In the following operation descriptions wait times after setting or clearing individual bits in FLMCR1 are given as para...

Page 821: ...g enable state 4 After a transition from program mode to the program setup state do not enter program mode without passing through the software programming enable state ESU1 0 ESU1 1 PSU1 1 PSU1 0 PV1 1 PV1 0 EV1 0 EV1 1 Figure 22 10 FLMCR1 Bit Settings and State Transitions 22 7 1 Program Mode When writing data or programs to flash memory the program program verify flowchart shown in figure 22 11...

Page 822: ... P1 bit in FLMCR1 then wait for at least α µs before clearing the PSU1 bit to exit program mode After the elapse of at least β µs the watchdog timer is cleared and the operating mode is switched to program verify mode by setting the PV1 bit in FLMCR1 Before reading in program verify mode a dummy write of H FF data should be made to the addresses to be read The dummy write should be executed after ...

Page 823: ...ation a verify read is performed in program verify mode and programming is judged to have been completed for bits read as 0 c If programming of other bits is incomplete in the 128 bytes reprogramming processing should be executed If a bit for which programming has been judged to be completed is read as 1 in a subsequent verify read a write pulse should again be applied to that bit 5 The period for...

Page 824: ...cuted 0 1 1 Programming by write pulse application incomplete additional programming processing not to be executed 1 0 1 Programming already completed additional programming processing not to be executed 1 1 1 Still in erased state no action Legend Y Data of bits on which additional programming is executed X Data of bits on which reprogramming is executed in a certain reprogramming loop 7 It is ne...

Page 825: ... applied Reprogram data X means reprogram data when the write pulse is applied Original Data D 0 0 1 1 Verify Data V 0 1 0 1 Reprogram Data X 1 0 1 1 Comments Programming complete Programming is incomplete reprogramming should be performed Left in the erased state Write pulse application subroutine Programming must be executed in the erased state Do not perform additional programming on addresses ...

Page 826: ...it for at least α µs before clearing the ESU1 bit to exit erase mode After exiting erase mode the watchdog timer is cleared after the elapse of β µs or more The operating mode is then switched to erase verify mode by setting the EV1 bit in FLMCR1 Before reading in erase verify mode a dummy write of H FF data should be made to the addresses to be read The dummy write should be executed after the el...

Page 827: ... bit in FLMCR1 Clear SWE1 bit in FLMCR1 Disable WDT Halt erase 1 Verify data all 1 Last address of block End of erasing of all erase blocks Erase failure Clear SWE1 bit in FLMCR1 n N NG NG NG NG OK OK OK OK n n 1 Increment address Wait 1 µs Wait 1 µs Notes 1 Preprogramming setting erase block data to all 0 is not necessary 2 Verify data is read in 16 bit W units 3 Set only one bit in EBR1 and 2 Mo...

Page 828: ...otected state See table 22 8 Table 22 8 Hardware Protection Functions Item Description Program Erase FWE pin protection When a low level is input to the FWE pin FLMCR1 FLMCR2 except bit FLER EBR1 and EBR2 are initialized and the program erase protected state is entered Yes Yes Reset standby protection In a power on reset including a WDT power on reset and in standby mode FLMCR1 FLMCR2 EBR1 and EBR...

Page 829: ...ction Functions Item Description Program Erase SWE bit protection Setting bit SWE1 in FLMCR1 to 0 will place area H 000000 to H 03FFFF in the program erase protected state Execute the program in the on chip RAM external memory Yes Yes Block specification protection Erase protection can be set for individual blocks by settings in erase block register 1 EBR1 and erase block register 2 EBR2 Setting E...

Page 830: ...d EBR2 settings are retained but program mode or erase mode is aborted at the point at which the error occurred Program mode or erase mode cannot be re entered by re setting the P1 or E1 bit However PV1 and EV1 bit setting is enabled and a transition can be made to verify mode FLER bit setting conditions are as follows 1 When the flash memory of the relevant address area is read during programming...

Page 831: ...ction mode software standby Software standby mode FLMCR1 FLMCR2 except bit FLER EBR1 EBR2 initialization state FLMCR1 FLMCR2 EBR1 EBR2 initialization state Software standby mode release RD Memory read possible VF Verify read possible PR Programming possible ER Erasing possible RD Memory read not possible VF Verify read not possible PR Programming not possible ER Erasing not possible Legend RES 0 o...

Page 832: ...esses cannot be made from the flash memory area or the RAM area overlapping flash memory Emulation can be performed in user mode and user program mode Figure 22 14 shows an example of emulation of real time flash memory programming Start of emulation program End of emulation program Tuning OK Yes No Set RAMER Write tuning data to overlap RAM Execute application program Clear RAMER Write to flash m...

Page 833: ...n confirmed the RAMS bit is cleared releasing RAM overlap 4 The data written in the overlapping RAM is written into the flash memory space EB0 Notes 1 When the RAMS bit is set to 1 program erase protection is enabled for all blocks regardless of the value of RAM2 to RAM0 emulation protection In this state setting the P1 or E1 bit in flash memory control register 1 FLMCR1 will not cause a transitio...

Page 834: ... interrupt is also disabled in the error protection state while the P1 or E1 bit remains set in FLMCR1 Notes 1 Interrupt requests must be disabled inside and outside the MCU until the programming control program has completed programming 2 The vector may not be read correctly in this case for the following two reasons If flash memory is read while being programmed or erased while the P1 or E1 bit ...

Page 835: ...rcuit XTAL EXTAL PLLVCC PLLCAP PLLVSS pins Oscillator circuit 22 11 1 Socket Adapter Pin Correspondence Diagram Connect the socket adapter to the chip as shown in figure 22 17 This will enable conversion to a 40 pin arrangement The on chip ROM memory map is shown in figure 22 16 and the socket adapter pin correspondence diagram in figure 22 17 H 000000 Addresses in MCU mode Addresses in programmer...

Page 836: ...1 40 11 30 5 6 7 8 9 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 I O0 I O1 I O2 I O3 I O4 I O5 I O6 I O7 CE OE WE FWE VCC VSS NC A20 A19 71 75 77 68 69 70 Other than the above 79 83 85 76 77 78 Other than the above RES XTAL EXTAL PLL VCC PLLCAP PLL VSS NC OPEN VCC VSS Power on reset circuit Oscillator circuit PLL circuit Legend FWE Flash write enable I O7 I O0 Data input outp...

Page 837: ... end of auto programming Status Read Mode Status polling is used for auto programming and auto erasing and normal termination can be confirmed by reading the I O6 signal In status read mode error information is output if an error occurs Table 22 11 Settings for Various Operating Modes In Programmer Mode Pin Names Mode FWE CE OE WE I O7 I O0 A18 A0 Read H or L L L H Data output Ain Output disable H...

Page 838: ...se status read operations a transition is made to the command wait state When reading memory contents a transition to memory read mode must first be made with a command write after which the memory contents are read 2 In memory read mode command writes can be performed in the same way as in the command wait state 3 Once memory read mode has been entered consecutive reads can be performed 4 After p...

Page 839: ... for Memory Read after Memory Write Table 22 14 AC Characteristics in Transition from Memory Read Mode to Another Mode Conditions VCC 3 3 V 0 3 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Command write cycle tnxtc 20 µs CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns WE rise time tr 30 ns WE fall time tf 30 ns ...

Page 840: ...o Another Mode Table 22 15 AC Characteristics in Memory Read Mode Conditions VCC 3 3 V 0 3 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Access time tacc 20 µs CE output delay time tce 150 ns OE output delay time toe 150 ns Output disable delay time tdf 100 ns Data output hold time toh 5 ns CE A18 A0 OE WE I O7 I O0 VIL VIL VIH tacc tacc toh toh Address stable Address stable Figure 22 20 CE and O...

Page 841: ... a memory write operation but a write error will be flagged 4 Memory address transfer is performed in the second cycle figure 22 22 Do not perform transfer after the third cycle 5 Do not perform a command write during a programming operation 6 Perform one auto program operation for a 128 byte block for each address Two or more additional programming operations cannot be performed on a previously p...

Page 842: ... Status polling access time tspa 150 ns Address setup time tas 0 ns Address hold time tah 60 ns Memory write time twrite 1 3000 ms Write setup time tpns 100 ns Write end setup time tpnh 100 ns WE rise time tr 30 ns WE fall time tf 30 ns CE A18 A0 FWE OE WE I O7 I O6 I O5 I O0 tpns twep tds tdh tf tr tas tah twsts twrite tspa tces tceh tnxtc tnxtc tpnh Address stable H 40 H 00 Data transfer 1 to 12...

Page 843: ...write As long as the next command write has not been performed reading is possible by enabling CE and OE Table 22 17 AC Characteristics in Auto Erase Mode Conditions VCC 3 3 V 0 3 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Command write cycle tnxtc 20 µs CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns Status polling...

Page 844: ...WE OE WE I O7 I O6 I O5 I O0 tens twep tds tdh tf tr tests terase tspa tces tceh tnxtc tnxtc tenh H 20 H 20 H 00 Erase end decision signal Erase normal end decision signal Figure 22 23 Auto Erase Mode Timing Waveforms ...

Page 845: ...0 3 V VSS 0 V Ta 25 C 5 C Item Symbol Min Max Unit Read time after command write tnxtc 20 µs CE hold time tceh 0 ns CE setup time tces 0 ns Data hold time tdh 50 ns Data setup time tds 50 ns Write pulse width twep 70 ns OE output delay time toe 150 ns Disable delay time tdf 100 ns CE output delay time tce 150 ns WE rise time tr 30 ns WE fall time tf 30 ns CE A18 A0 OE WE I O7 I O0 twep tf tr toe t...

Page 846: ...ag indicates the operating status in auto program auto erase mode 2 The I O6 status polling flag indicates a normal or abnormal end in auto program auto erase mode Table 22 20 Status Polling Output Truth Table Pin Name During Internal Operation Abnormal End Normal End I O7 0 1 0 1 I O6 0 0 1 1 I O0 I O5 0 0 0 0 22 11 8 Programmer Mode Transition Time Commands cannot be accepted during the oscillat...

Page 847: ...d carry out auto erasing before auto programming 2 When performing programming using programmer mode on a chip that has been programmed erased in an on board programming mode auto erasing is recommended before carrying out auto programming Notes 1 The flash memory is initially in the erased state when the device is shipped by Hitachi For other chips for which the erasure history is unknown it is r...

Page 848: ...perating states of the H8S 2633 and the flash memory Table 22 22 Flash Memory Operating States LSI Operating State Flash Memory Operating State High speed mode Medium speed mode Sleep mode Normal mode read write Subactive mode Subsleep mode When PDWND 0 Power down mode read only When PDWND 1 Normal mode read only Watch mode Software standby mode Hardware standby mode Standby mode 22 12 1 Note on P...

Page 849: ... off timing requirements should also be satisfied in the event of a power failure and subsequent recovery FWE application disconnection see figures 22 26 to 22 28 FWE application should be carried out when MCU operation is in a stable condition If MCU operation is not stable fix the FWE pin low and set the protection state The following points must be observed concerning FWE application and discon...

Page 850: ...ations verification during programming erasing Also do not clear the SWE1 bit during programming erasing or verifying Similarly when using the RAM emulation function while a high level is being input to the FWE pin the SWE1 bit must be cleared before executing a program or reading data in flash memory However the RAM area overlapping flash memory space can be read and written to regardless of whet...

Page 851: ...tions prohibited ø VCC FWE tOSC1 Min 0 µs Min 0 µs tMDS 3 tMDS 3 MD2 to MD0 1 RES SWE1 bit SWE1 set SWE1 cleared Programming erasing possible Wait time x Wait time 100 µs Notes 1 Except when switching modes the level of the mode pins MD2 to MD0 must be fixed until power off by pulling the pins up or down 2 See 25 6 Flash Memory Characteristics 3 Mode programming setup time tMDS min 200 ns Figure 2...

Page 852: ...it 2 Period during which flash memory can be programmed Execution of program in flash memory prohibited and data reads other than verify operations prohibited Notes 1 Except when switching modes the level of the mode pins MD2 to MD0 must be fixed until power off by pulling the pins up or down 2 See 25 6 Flash Memory Characteristics 3 Mode programming setup time tMDS min 200 ns Figure 22 27 Power O...

Page 853: ...00 µs Programming erasing possible Wait time x Wait time 100 µs User mode User program mode Notes 1 When entering boot mode or making a transition from boot mode to another mode mode switching must be carried out by means of RES input The state of ports with multiplexed address functions and bus control output pins AS RD WR will change during this switchover interval the interval during which the ...

Page 854: ...mask ROM version an undefined value will be returned Therefore if application software developed on the F ZTAT version is switched to a mask ROM version product it must be modified to ensure that the registers in table 22 23 have no effect Table 22 23 Registers Present in F ZTAT Version but Absent in Mask ROM Version Register Abbreviation Address Flash memory control register 1 FLMCR1 H FFC8 Flash...

Page 855: ...erformed by software by means of settings in the system clock control register SCKCR and low power control register LPWRCR 23 1 1 Block Diagram Figure 23 1 shows a block diagram of the clock pulse generator Legend LPWRCR SCKCR Low power control register System clock control register EXTAL XTAL PLL circuit 1 2 4 Medium speed clock divider System clock oscillator Clock selection circuit ø SUB WDT1 c...

Page 856: ... value R W SCKCR is an 8 bit readable writable register that performs ø clock output control selection of operation when the PLL circuit frequency multiplication factor is changed and medium speed mode control SCKCR is initialized to H 00 by a reset and in hardware standby mode It is not initialized in software standby mode Bit 7 ø Clock Output Disable PSTOP Controls ø output Description Bit 7 PST...

Page 857: ...0 Description 0 0 0 Bus master is in high speed mode Initial value 1 Medium speed clock is ø 2 1 0 Medium speed clock is ø 4 1 Medium speed clock is ø 8 1 0 0 Medium speed clock is ø 16 1 Medium speed clock is ø 32 1 23 2 2 Low Power Control Register LPWRCR 7 DTON 0 R W 6 LSON 0 R W 5 NESEL 0 R W 4 SUBSTP 0 R W 3 RFCUT 0 R W 0 STC0 0 R W 2 0 R W 1 STC1 0 R W Bit Initial value R W LPWRCR is an 8 bi...

Page 858: ... connecting a crystal resonator or by input of an external clock 23 3 1 Connecting a Crystal Resonator Circuit Configuration A crystal resonator can be connected as shown in the example in figure 23 2 Select the damping resistance Rd according to table 23 2 An AT cut parallel resonance crystal should be used EXTAL XTAL Rd CL2 CL1 CL1 CL2 10 to 22pF Figure 23 2 Connection of Crystal Resonator Examp...

Page 859: ...n When a crystal resonator is connected the following points should be noted Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation See figure 23 4 When designing the board place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins CL2 Signal A Signal B CL1 H8S 2633 Series XTAL EXT...

Page 860: ...s are recommended values Figure 23 5 Points for Attention when Using PLL Oscillation Circuit Place oscillation stabilization capacitor C1 and resistor R1 close to the PLLCAP pin and ensure that no other signal lines cross this line Supply the C1 ground from PLLVSS Separate PLLVCC and PLLVSS from the other VCC and VSS lines at the board power supply source and be sure to insert bypass capacitors CP...

Page 861: ... If the XTAL pin is left open make sure that stray capacitance is no more than 10 pF In example b make sure that the external clock is held high in standby mode EXTAL XTAL External clock input Open a XTAL pin left open EXTAL XTAL External clock input b Complementary clock input at XTAL pin Figure 23 6 External Clock Input Examples ...

Page 862: ...st Conditions External clock input low pulse width tEXL 20 15 ns Figure 23 7 External clock input high pulse width tEXH 20 15 ns External clock rise time tEXr 10 5 ns External clock fall time tEXf 10 5 ns Clock low pulse width level tCL 0 4 0 6 0 4 0 6 tcyc ø 5 MHz Figure 25 2 80 80 ns ø 5 MHz Clock high pulse width level tCH 0 4 0 6 0 4 0 6 tcyc ø 5 MHz 80 80 ns ø 5 MHz tEXH tEXL tEXr tEXf VCC 0 ...

Page 863: ...ftware standby mode watch mode or subactive mode 4 The clock pulse generator stops and the value set in STC1 and STC0 becomes valid 5 Software standby mode watch mode or subactive mode is cleared and a transition time is secured in accordance with the setting in STS2 to STS0 6 After the set transition time has elapsed the LSI resumes operation using the target multiplication factor If a PC break i...

Page 864: ...on 23 3 1 Notes on Board Design for notes on connecting crystal oscillators OSC1 OSC2 C1 C2 C1 C2 15pF typ Figure 23 8 Example Connection of 32 768kHz Crystal Oscillator Figure 23 9 shows the equivalence circuit for a 32 768kHz oscillator OSC1 OSC2 Cs Ls Rs Co Co 1 5pF typ Rs 14kΩ typ fw 32 768kHz Type No MX38T Nihon Dempa Kogyo Figure 23 9 Equivalence Circuit for 32 768kHz Oscillator ...

Page 865: ... No sampling is performed in sub active mode sub sleep mode or watch mode 23 9 Note on Crystal Resonator Since various characteristics related to the crystal resonator are closely linked to the user s board design thorough evaluation is necessary on the user s part for both the mask versions and F ZTAT versions using the resonator connection examples shown in this section as a guide As the resonat...

Page 866: ... Module stop mode 8 Software standby mode 9 Hardware standby mode 2 to 9 are power down modes Sleep mode and sub sleep mode are CPU mode medium speed mode is a CPU and bus master mode sub active mode is a CPU and bus master and on chip supporting module mode and module stop mode is an on chip supporting module mode including bus masters other than the CPU state Some of these modes can be combined ...

Page 867: ...ng Function ing Function ing Function ing Halted retained Subclock operation Subclock operation Halted retained Halted reset TMR Halted retained DMAC Function Medium Function Halted Halted Halted Halted Halted Halted DTC ing speed operation ing retained retained retained retained retained reset TPU Function Function Function Halted Halted Halted Halted Halted Halted IIC0 ing ing ing retained retai...

Page 868: ...e main clock Medium speed mode main clock Sub active mode subclock Sub sleep mode subclock Hardware standby mode Software standby mode Sleep mode main clock Watch mode subclock Notes 1 2 3 4 NMI IRQ0 to IRQ7 and WDT1 interrupts NMI IRQ0 to IRQ7 IWDT0 interrupts WDT1 interrupt and TMR0 to TMR3 interrupts All interrupts NMI and IRQ0 to IRQ7 When a transition is made between modes by means of an inte...

Page 869: ...nvoked by State SSBY PSS LSON DTON Command Interrupt High speed 0 0 Sleep High speed Medium speed Medium speed 0 1 1 0 0 Software standby High speed Medium speed 1 0 1 1 1 0 0 Watch High speed 1 1 1 0 Watch Sub active 1 1 0 1 1 1 1 1 Sub active Sub active 0 0 0 1 0 0 1 1 Sub sleep Sub active 1 0 1 1 0 0 Watch High speed 1 1 1 0 Watch Sub active 1 1 0 1 High speed 1 1 1 1 Don t care Do not set ...

Page 870: ...gisters Name Abbreviation R W Initial Value Address Standby control register SBYCR R W H 08 H FDE4 System clock control register SCKCR R W H 00 H FDE6 Low power control register LPWRCR R W H 00 H FDEC Timer control status register TCSR R W H 00 H FFA2 Module stop control register MSTPCRA R W H 3F H FDE8 A B C MSTPCRB R W H FF H FDE9 MSTPCRC R W H FF H FDEA Note Lower 16 bits of the address ...

Page 871: ... the SLEEP instruction the operating mode is determined in combination with other control bits Note that the value of the SSBY bit does not change even when shifting between modes using interrupts Bit 7 SSBY Description 0 Shifts to sleep mode when the SLEEP instruction is executed in high speed mode or medium speed mode Shifts to sub sleep mode when the SLEEP instruction is executed in sub active ...

Page 872: ...tandby time 32768 states 1 Standby time 65536 states 1 0 0 Standby time 131072 states 1 Standby time 262144 states 1 0 Reserved 1 Standby time 16 states Bit 3 Output Port Enable OPE This bit specifies whether the output of the address bus and bus control signals CS0 to CS7 AS RD HWR LWR CAS OE is retained or set to high impedance state in the software standby mode watch mode and when making a dire...

Page 873: ...tion 24 12 ø Clock Output Disabling Function for details Description Bit 7 PSTOP High Speed Mode Medium Speed Mode Sub Active Mode Sleep Mode Sub Sleep Mode Software Standby Mode Watch Mode Hardware Standby Mode 0 ø output initial value ø output Fixed high High impedance 1 Fixed high Fixed high Fixed high High impedance Bits 6 and 4 Reserved These bits are always read as 0 and cannot be modified B...

Page 874: ... W 0 STC0 0 R W 2 0 R W 1 STC1 0 R W Bit Initial value R W The LPWRCR is an 8 bit read write register that controls the low power dissipation modes The LPWRCR is initialized to H 00 at a power on reset and when in hardware standby mode It is not initialized at a manual reset or when in software standby mode The following describes bits 7 to 2 For details of other bits see Section 23 2 2 Low Power ...

Page 875: ...by executing the SLEEP instruction this bit specifies the operating mode in combination with other control bits This bit also controls whether to shift to high speed mode or sub active mode when watch mode is cancelled Bit 6 LSON Description 0 When the SLEEP instruction is executed in high speed mode or medium speed mode operation shifts to sleep mode software standby mode or watch mode When the S...

Page 876: ...nable SUBSTP This bit enables disables subclock generation Bit 4 SUBSTP Description 0 Enables subclock generation Initial value 1 Disables subclock generation Bit 3 Oscillation Circuit Feedback Resistance Control Bit RFCUT This bit turns the internal feedback resistance of the main clock oscillation circuit ON OFF Bit 3 RFCUT Description 0 When the main clock is oscillating sets the feedback resis...

Page 877: ...ipation modes The operating mode selected after the SLEEP instruction is executed is determined in combination with other control bits For details see the description for clock selection in Section 15 2 2 Timer Control Status Register TCSR and this section Bit 4 PSS Description 0 TCNT counts the divided clock from the ø based prescaler PSM When the SLEEP instruction is executed in high speed mode ...

Page 878: ...W R W R W R W MSTPCR comprising three 8 bit readable writable registers performs module stop mode control MSTPCR is initialized to H 3FFFFF by a reset and in hardware standby mode It is not initialized in software standby mode MSTPCRA MSTPCRB MSTPCRC Bits 7 to 0 Module Stop MSTPA7 to MSTPA0 MSTPB7 to MSTPB0 MSTPC7 to MSTPC0 These bits specify module stop mode See table 24 3 for the method of selec...

Page 879: ...ed by clearing all of bits SCK2 to SCK0 to 0 A transition is made to high speed mode and medium speed mode is cleared at the end of the current bus cycle If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0 and LSON bit in LPWRCR is cleared to 0 a transition is made to sleep mode When sleep mode is cleared by an interrupt medium speed mode is restored When the SLEEP instru...

Page 880: ...2 Exiting Sleep Mode Sleep mode is exited by any interrupt or signals at the RES MRES or STBY pins 1 Exiting Sleep Mode by Interrupts When an interrupt occurs sleep mode is exited and interrupt exception processing starts Sleep mode is not exited if the interrupt is disabled or interrupts other than NMI are masked by the CPU 2 Exiting Sleep Mode by RES or MRES Pins Setting the RES or MRES pin leve...

Page 881: ...y Table 24 4 shows MSTP bits and the corresponding on chip supporting modules When the corresponding MSTP bit is cleared to 0 module stop mode is cleared and the module starts operating at the end of the bus cycle In module stop mode the internal states of modules other than the SCI A D converter and 14 bit PWM are retained After reset clearance all modules other than DMAC and DTC are in module st...

Page 882: ... timer TMR2 TMR3 MSTPCRB MSTPB7 Serial communication interface 0 SCI0 MSTPB6 Serial communication interface 1 SCI1 MSTPB5 Serial communication interface 2 SCI2 MSTPB4 I2 C bus interface 0 IIC0 MSTPB3 I2 C bus interface 1 IIC1 MSTPB2 14 bit PWM timer PWM0 MSTPB1 14 bit PWM timer PWM1 MSTPB0 MSTPCRC MSTPC7 Serial communication interface 3 SCI3 MSTPC6 Serial communication interface 4 SCI4 MSTPC5 D A ...

Page 883: ...ing modules and oscillator all stop However the contents of the CPU s internal registers RAM data and the states of on chip supporting modules other than the SCI A D converter and 14 bit PWM and I O ports are retained Whether the address bus and bus control signals are placed in the high impedance state In this mode the oscillator stops and therefore power dissipation is significantly reduced 24 6...

Page 884: ...cillator Set bits STS2 to STS0 so that the standby time is at least 8 ms the oscillation stabilization time Table 24 5 shows the standby times for different operating frequencies and settings of bits STS2 to STS0 Table 24 5 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 25 MHz 20 MHz 16 MHz 12 MHz 10 MHz 8 MHz 6 MHz 4 MHz 2 MHz Unit 0 0 0 8192 states 0 32 0 41 0 51 0 65 0 8 1 ...

Page 885: ...MI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 falling edge specification then the NMIEG bit is set to 1 rising edge specification the SSBY bit is set to 1 and a SLEEP instruction is executed causing a transition to software standby mode Software standby mode is then cleared at the rising edge on the NMI pin Oscillator ø NMI NMIEG SSBY NMI exception handling NMIEG 1 SSBY 1 SLEEP...

Page 886: ...e write data buffer function 24 7 Hardware Standby Mode 24 7 1 Hardware Standby Mode When the STBY pin is driven low a transition is made to hardware standby mode from any mode In hardware standby mode all functions enter the reset state and stop operation resulting in a significant reduction in power dissipation As long as the prescribed voltage is supplied on chip RAM data is retained I O ports ...

Page 887: ...STBY Oscillation stabilization time Reset exception handling Figure 24 4 Hardware Standby Mode Timing 24 8 Watch Mode 24 8 1 Watch Mode CPU operation makes a transition to watch mode when the SLEEP instruction is executed in high speed mode or sub active mode with SBYCR SSBY 1 LPWRCR DTON 0 and TCSR WDT1 PSS 1 In watch mode the CPU is stopped and supporting modules other than WDT1 are also stopped...

Page 888: ...ion of that interrupt or is masked by the CPU See Section 24 6 3 Setting Oscillation Stabilization Time After Clearing Software Standby Mode for how to set the oscillation stabilization time when making a transition from watch mode to high speed mode 2 Exiting Watch Mode by RES or MRES Pins For exiting watch mode by the RES or MRES pins see 2 Exiting Software Standby Mode by RES or MRES pins in Se...

Page 889: ...n or IRQ0 to IRQ7 or signals at the RES MRES or STBY pins 1 Exiting Sub Sleep Mode by Interrupts When an interrupt occurs sub sleep mode is exited and interrupt exception processing starts In the case of IRQ0 to IRQ7 interrupts sub sleep mode is not cancelled if the corresponding enable bit has been cleared to 0 and in the case of interrupts from the internal supporting modules the interrupt enabl...

Page 890: ...the RES MRES or STBY pins 1 Exiting Sub Active Mode by SLEEP Instruction When the SLEEP instruction is executed with the SBYCR SSBY bit 1 LPWRCR DTON bit 0 and TCSR WDT1 PSS bit 1 the CPU exits sub active mode and a transition is made to watch mode When the SLEEP instruction is executed with the SBYCR SSBY bit 0 LPWRCR LSON bit 1 and TCSR WDT1 PSS bit 1 a transition is made to sub sleep mode Final...

Page 891: ...YCR SSBY bit 1 LPWRCR LSON bit 0 and DTON bit 1 and TSCR WDT1 PSS bit 1 to make a direct transition to high speed mode after the time set in SBYCR STS2 to STS0 has elapsed 24 12 ø Clock Output Disabling Function Output of the ø clock can be controlled by means of the PSTOP bit in SCKCR and DDR for the corresponding port When the PSTOP bit is set to 1 the ø clock stops at the end of the bus cycle a...

Page 892: ... XTAL EXTAL OSC1 OSC2 Vin 0 3 to VCC 0 3 V Input voltage port 4 and 9 Vin 0 3 to AVCC 0 3 V Input voltage except XTAL EXTAL OSC1 OSC2 port 4 and 9 Vin 0 3 to PVCC 0 3 V Reference voltage Vref 0 3 to AVCC 0 3 V Analog power supply voltage AVCC 0 3 to 7 0 V Analog input voltage VAN 0 3 to AVCC 0 3 V Operating temperature Topr Regular specifications 20 to 75 C Wide range specifications 40 to 85 C Sto...

Page 893: ... 7 V voltage VT VT 0 4 V Input high voltage RES STBY NMI FWE MD2 to MD0 VIH PVCC 0 7 PVCC 0 3 V EXTAL OSC1 VCC 0 8 VCC 0 3 V Port 1 3 7 A toG 2 2 PVCC 0 3 V Port 4 and 9 AVCC 0 7 AVCC 0 3 V Input low voltage RES STBY NMI FWE MD2 to MD0 VIL 0 3 0 5 V EXTAL OSC1 0 3 VCC 0 2 V Port 1 3 4 7 9 A toG 0 3 0 8 V Output high voltage All output pins except P34 and P35 VOH PVCC 0 5 V IOH 200 µA P34 P35 PVCC ...

Page 894: ...tion 2 Normal operation ICC 4 72 VCC 3 3 V 85 VCC 3 6 V mA f 25 MHz Sleep mode 58 VCC 3 3 V 75 VCC 3 6 V mA f 25 MHz All modules stopped 50 mA f 25 MHz VCC 3 3 V reference values Medium speed mode ø 32 40 mA f 25 MHz VCC 3 3 V reference values Subactive mode 120 VCC 3 0 V Ta 25 C 200 µA Using 32 768 kHz crystal resonator Subsleep mode 70 VCC 3 0 V Ta 25 C 150 µA Using 32 768 kHz crystal resonator ...

Page 895: ...age VRAM 2 0 V Notes 1 If the A D and D A converters are not used do not leave the AVCC Vref and AVSS pins open Apply a voltage between 3 3 V and 5 5 V to the AVCC and Vref pins by connecting them to PVCC for instance Set Vref AVCC 2 Current dissipation values are for VIH VCC EXTAL OSC1 AVCC ports 4 and 9 or PVCC other and VIL 0 V with all output pins unloaded and the on chip MOS pull up transisto...

Page 896: ...D0 VIH PVCC 0 9 PVCC 0 3 V EXTAL OSC1 VCC 0 8 VCC 0 3 V Port 1 3 7 A to G PVCC 0 8 PVCC 0 3 V Port 4 and 9 AVCC 0 8 AVCC 0 3 V Input low voltage RES STBY NMI FWE MD2 to MD0 VIL 0 3 PVCC 0 1 V EXTAL OSC1 0 3 VCC 0 2 V Port 1 3 7 A to G 0 3 PVCC 0 2 V Port 4 and 9 0 3 AVCC 0 2 V Output high voltage All output pins except P34 and P35 VOH PVCC 0 5 V IOH 200 µA P34 P35 PVCC 2 5 IOH 100 µA 2 All output ...

Page 897: ...ion 3 Normal operation ICC 5 40 VCC 3 3 V 60 VCC 3 6 V mA f 16 MHz Sleep mode 35 VCC 3 3 V 45 VCC 3 6 V mA f 16 MHz All modules stopped 30 mA f 16 MHz VCC 3 3 V reference values Medium speed mode ø 32 25 mA f 16 MHz VCC 3 3 V reference values Subactive mode 120 VCC 3 0 V T a 25 C 200 µA Using 32 768 kHz crystal resonator Subsleep mode 70 VCC 3 0 V T a 25 C 150 µA Using 32 768 kHz crystal resonator...

Page 898: ... D A converters are not used do not leave the AVCC Vref and AVSS pins open Apply a voltage between 3 3 V to 5 5 V to the AVCC and Vref pins by connecting them to PVCC for instance Set Vref AVCC 2 When using P34 and P35 as output pins set PVCC 4 5 V to 5 5 V 3 Current dissipation values are for VIH VCC EXTAL OSC1 AVCC ports 4 and 9 or PVCC other and VIL 0 V with all output pins unloaded and the on ...

Page 899: ... Typ Max Unit Permissible output low current per pin All output pins PVCC 3 0 to 5 5 V IOL 10 mA Permissible output low current total Total of all output pins PVCC 3 0 to 5 5 V IOL 120 mA Permissible output high current per pin All output pins PVCC 3 0 to 5 5 V IOH 2 0 mA Permissible output high current total Total of all output pins PVCC 3 0 to 5 5 V IOH 40 mA Note To protect chip reliability do ...

Page 900: ...est Conditions Schmitt trigger VT PVCC 0 3 V input voltage VT PVCC 0 7 VT VT 0 4 PVCC 4 5 V to 5 5V 0 2 PVCC 3 0 V to 4 5V Input high voltage VIH PVCC 0 7 PVCC 0 5 V Input low voltage VIL 0 5 PVCC 0 3 V Output low voltage VOL 0 7 IOL 8 mA PVCC 4 5 V to 5 5 V 0 4 IOL 3 mA PVCC 4 5 V to 5 5 V 0 4 IOL 1 6 mA PVCC 3 0 V to 5 5 V Input capacitance Cin 20 pF Vin 0V f 1MHz Ta 25 C Three state leakage cur...

Page 901: ...aracteristics 5 V RL RH C LSI output pin C 50 pF Ports 10 to 13 70 to 73 A to G In case of expansion bus control signal output pin setting C 30 pF All ports RL 2 4 kΩ RH 12 kΩ Input output timing measurement levels Low level 0 8 V High level 2 0 V Figure 25 1 Output Load Circuit ...

Page 902: ...C to 85 C wide range specifications Condition A Condition B 16MHz 25MHz Item Symbol Min Max Min Max Unit Test Conditions Clock cycle time tcyc 62 5 500 40 500 ns Figure 25 2 Clock high pulse width tCH 18 15 ns Clock low pulse width tCL 18 15 ns Clock rise time tCr 12 5 ns Clock fall time tCf 12 5 ns Clock oscillator settling time at reset crystal tOSC1 10 10 ms Figure 25 3 Clock oscillator settlin...

Page 903: ...890 tCH tCf tcyc tCL tCr ø Figure 25 2 System Clock Timing tOSC1 tOSC1 EXTAL VCC STBY RES ø tDEXT tDEXT Figure 25 3 Oscillator Settling Timing ...

Page 904: ... 3 3 V to AVCC VSS AVSS 0 V ø 32 768 kHz 2 to 25 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions RES setup time tRESS 200 200 ns Figure 25 4 RES pulse width tRESW 20 20 tcyc MRES setup time tMRESS 250 250 ns MRES pulse width tMRESW 20 20 tcyc NMI setup time tNMIS 250 150 ns Figure 25 5 NMI...

Page 905: ...892 tRESW tRESS tMRESS tMRESS tMRESW ø tRESS RES MRES Figure 25 4 Reset Input Timing ø tIRQS IRQ Edge input tIRQH tNMIS tNMIH tIRQS IRQ Level input NMI IRQ tNMIW tIRQW Figure 25 5 Interrupt Input Timing ...

Page 906: ...ations Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions Address delay time tAD 30 20 ns Figure 25 6 to Address setup time tAS 0 5 tcyc 30 0 5 tcyc 15 ns Figure 25 11 Address hold time tAH 0 5 tcyc 20 0 5 tcyc 8 ns CS delay time 1 tCSD1 30 20 ns CS delay time 2 tCSD2 30 18 ns AS delay time tASD 30 18 ns RD delay time 1 tRSD1 30 18 ns RD delay time 2 tRSD2 30 18 ns Read data ...

Page 907: ... WR setup time tWCS 0 5 tcyc 15 0 5 tcyc 10 ns WR hold time tWCH 0 5 tcyc 15 0 5 tcyc 10 ns RAS precharge time tPCH 1 5 tcyc 30 1 5 tcyc 15 ns Figure 25 11 to Figure 25 13 CAS precharge time1 tCP1 1 0 tcyc 20 1 0 tcyc 8 ns CAS precharge time2 tCP2 0 5 tcyc 20 0 5 tcyc 8 ns CAS delay time1 tCASD1 30 20 ns CAS delay time2 tCASD2 30 18 ns OE delay time1 tOED1 30 18 ns OE delay time2 tOED2 30 18 ns CA...

Page 908: ...tAD AS A23 to A0 tASD RD read CS7 to CS0 T2 tAS tASD tACC2 tRSD1 tACC3 tRDS tRDH tWRD2 tWDD tWSW1 tWDH D15 to D0 read WR write D15 to D0 write tAH tWRD2 tCSD1 tAS tAH tAS Figure 25 6 Basic Bus Timing Two State Access ...

Page 909: ...A23 to A0 tASD RD read T3 tAS tAS tAH tASD tACC4 tRSD1 tACC5 tRDS tRDH tWRD1 tWRD2 tWDS tWSW2 tWDH tAH D15 to D0 read WR write D15 to D0 write T1 tWDD tAD tCSD1 CS7 to CS0 Figure 25 7 Basic Bus Timing Three State Access ...

Page 910: ...897 ø TW AS A23 to A0 RD read T3 D15 to D0 read WR write D15 to D0 write CS7 to CS0 T2 tWTS T1 tWTH tWTS tWTH WAIT Figure 25 8 Basic Bus Timing Three State Access with One Wait State ...

Page 911: ...898 tRSD2 ø T1 AS A23 to A0 T2 tAH tACC3 tRDS D15 to D0 read T2 or T3 tAS T1 tASD tASD tRDH tAD CS7 to CS0 RD read Figure 25 9 Burst ROM Access Timing Two State Access ...

Page 912: ...899 ø T1 AS A23 to A0 T1 tACC1 D15 to D0 read T2 or T3 tRDH tAD CS7 to CS0 RD read tRDS tRSD2 Figure 25 10 Burst ROM Access Timing One State Access ...

Page 913: ...CASD1 tCASD1 tACC1 tCASD1 tCP1 tCP2 tAH ø A23 to A0 D15 to D0 read CS5 to CS2 RAS HWR LWR write CAL LCAS RCTS 0 CAL to LCAS When RCTS is set to 1 read OE When OES is set to 1 read D15 to D0 write Figure 25 11 DRAM Access Timing tCASD1 TRC1 TRC2 TRr TRp ø CS5 to CS2 RAS CAS LCAS tCSD2 tCSR tCSD1 tCASD1 Figure 25 12 DRAM CBR Refresh Timing ...

Page 914: ... tCSD2 tCSR tCSD2 tCASD1 Figure 25 13 DRAM Self Refresh Timing ø BREQ BACK A23 to A0 CS7 to CS0 AS RD HWR LWR tBZD tBZD tBACD tBACD tBRQS tBRQS Figure 25 14 External Bus Release Timing ø BREQO tBRQOD tBRQOD Figure 25 15 External Bus Request Output Timing ...

Page 915: ...ons Condition B VCC PLLVCC 3 0 V to 3 6 V PVCC 4 5 V to 5 5 V AVCC 3 3 V to 5 5 V Vref 3 3 V to AVCC VSS AVSS 0 V ø 2 to 25 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions DREQ setup time tDRQS 40 25 ns Figure 25 19 DREQ hold time tDRQH 10 10 TEND delay time tTED 30 20 Figure 25 18 DACK de...

Page 916: ...903 ø A23 to A0 AS CS7 to CS0 T1 T2 RD read D15 to D0 read D15 to D0 write HWR to LWR DACK0 DACK1 tDACD1 tDACD2 Figure 25 16 DMAC Single Address Transfer Timing Two State Access ...

Page 917: ...CS0 T1 T2 RD read D15 to D0 read D15 to D0 write HWR to LWR DACK0 DACK1 tDACD1 tDACD2 T2 Figure 25 17 DMAC Single Address Transfer Timing Three State Access ø TEND0 TEND1 T1 T2 orT3 tTED tTED Figure 25 18 DMAC TEND Output Timing ...

Page 918: ...905 ø DREQ0 DREQ1 tDRQS tDRQH Figure 25 19 DMAC DREQ Input Timing ...

Page 919: ...3 3 V to 5 5 V Vref 3 3 V to AVCC VSS AVSS 0 V ø 32 768 kHz 2 to 25 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions I O port Output data delay time tPWD 60 40 ns Figure 25 20 Input data setup time tPRS 40 25 Input data hold time tPRH 40 25 PPG Pulse output delay time tPOD 60 40 ns Figure 2...

Page 920: ...5 27 WDT1 Buzz output delay time tBUZD 60 40 ns Figure 25 28 PWM Pulse output delay time tPWOD 60 40 ns Figure 25 29 SCI Input clock Asynchro nous tScyc 4 4 tcyc Figure 25 30 cycle Synchro nous 6 6 Input clock pulse width tSCKW 0 4 0 6 0 4 0 6 tScyc Input clock rise time tSCKr 1 5 1 5 tcyc Input clock fall time tSCKf 1 5 1 5 Transmit data delay time tTXD 60 40 ns Figure 25 31 Receive data setup ti...

Page 921: ...7 A to G write Figure 25 20 I O Port Input Output Timing ø PO 15 to 8 tPOD Figure 25 21 PPG Output Timing ø tTICS tTOCD Output compare output Input capture input Note TIOCA0 to TIOCA5 TIOCB0 to TIOCB5 TIOCC0 TIOCC3 TIOCD0 TIOCD3 Figure 25 22 TPU Input Output Timing ...

Page 922: ...ure 25 23 TPU Clock Input Timing ø tTMOD TMO0 TMO1 TMO2 TMO3 Figure 25 24 8 bit Timer Output Timing tTMCS ø tTMCS TMCI01 TMCI23 tTMCWH tTMCWL Figure 25 25 8 bit Timer Clock Input Timing ø tTMRS TMRI01 TMRI23 Figure 25 26 8 bit Timer Reset Input Timing ...

Page 923: ...VD WDTOVF Figure 25 27 WDT0 Output Timing ø tBUZD BUZZ tBUZD Figure 25 28 WDT1 Output Timing ø PWM3 toPWM0 tPWOD Figure 25 29 PWM Output Timing SCK0 to SCK4 tSCKW tSCKr tSCKf tScyc Figure 25 30 SCK Clock Input Timing ...

Page 924: ...D0 to TxD4 transit data RxD0 to RxD4 receive data SCK0 to SCK4 tRXS tRXH tTXD Figure 25 31 SCI Input Output Timing Clock Synchronous Mode ø ADTRG tTRGS Figure 25 32 A D Converter External Trigger Input Timing ...

Page 925: ... rise time tSr 7 5tcyc ns SCL SDA input fall time tSf 300 ns SCL SDA input spike pulse elimination time tSP 1tcyc ns SDA input bus free time tBUF 5tcyc ns Start condition input hold time tSTAH 3tcyc ns Retransmission start condition input setup time tSTAS 3tcyc ns Stop condition input setup time tSTOS 3tcyc ns Data input setup time tSDAS 0 5tcyc ns Data input hold time tSDAH 0 ns SCL SDA capacitiv...

Page 926: ... tSf tSr tSCL tSDAH tSDAS P S Sr VIH VIL SDA0 to SDA1 SCL0 to SCL1 Note S P and Sr indicate the following conditions S Start condition P Stop condition Sr Retransmission start condition Figure 25 33 I2 C Bus Inteface Input Output Timing Option ...

Page 927: ...Condition B VCC PLLVCC 3 0 V to 3 6 V PVCC 4 5 V to 5 5 V AVCC 4 5 V to 5 5 V Vref 4 5 V to AVCC VSS AVSS 0 V ø 2 to 25 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition A Condition B Item Min Typ Max Min Typ Max Unit Resolution 10 10 10 10 10 10 bits Conversion time 16 7 10 6 µs Analog input capacitance 20 20 pF Permissible signal source impedance 5 5 ...

Page 928: ...cations Ta 40 C to 85 C wide range specifications Condition B VCC PLLVCC 3 0 V to 3 6 V PVCC 4 5 V to 5 5 V AVCC 4 5 V to 5 5 V Vref 4 5 V to AVCC VSS AVSS 0 V ø 2 to 25 MHz Ta 20 C to 75 C regular specifications Ta 40 C to 85 C wide range specifications Condition A Condition B Item Min Typ Max Min Typ Max Unit Test Conditions Resolution 8 8 8 8 8 8 bits Conversion time 10 10 µs 20 pF capacitive l...

Page 929: ...setting 1 γ 4 µs Wait time after H FF dummy write 1 ε 2 µs Wait time after PV1 bit clearing 1 η 2 µs Maximum number of writes 1 4 N1 6 Times N2 994 Times Common Wait time after SWE1 bit clearing 1 x1 100 µs Erasing Wait time after SWE1 bit setting 1 x 1 µs Wait time after ESU1 bit setting 1 y 100 µs Wait time after E1 bit setting 1 5 z 10 ms Wait time after E1 bit clearing 1 α 10 µs Wait time afte...

Page 930: ...um number of erases N 25 7 Usage Note Although both the F ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual due to differences in the fabrication process the on chip ROM and the layout patterns there will be differences in the actual values of the electrical characteristics the operating margins the noise margins and other aspects Therefore if a system is ev...

Page 931: ...Z zero flag in CCR V V overflow flag in CCR C C carry flag in CCR PC Program counter SP Stack pointer IMM Immediate data disp Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Transfer from the operand on the left to the operand on the right or transition from the state on the left to the state on the right Logical NOT logical complement Contents of operand 8 16...

Page 932: ...920 Condition Code Notation Symbol Changes according to the result of instruction Undetermined no guaranteed value 0 Always cleared to 0 1 Always set to 1 Not affected by execution of the instruction ...

Page 933: ...B Rs ERd B 2 MOV B Rs d 16 ERd B 4 MOV B Rs d 32 ERd B 8 MOV B Rs ERd B 2 MOV B Rs aa 8 B 2 MOV B Rs aa 16 B 4 MOV B Rs aa 32 B 6 MOV W xx 16 Rd W 4 MOV W Rs Rd W 2 MOV W ERs Rd W 2 xx 8 Rd8 0 1 Rs8 Rd8 0 1 ERs Rd8 0 2 d 16 ERs Rd8 0 3 d 32 ERs Rd8 0 5 ERs Rd8 ERs32 1 ERs32 0 3 aa 8 Rd8 0 2 aa 16 Rd8 0 3 aa 32 Rd8 0 4 Rs8 ERd 0 2 Rs8 d 16 ERd 0 3 Rs8 d 32 ERd 0 5 ERd32 1 ERd32 Rs8 ERd 0 3 Rs8 aa 8...

Page 934: ...OV L ERs ERd L 2 MOV L ERs ERd L 4 MOV L d 16 ERs ERd L 6 MOV L d 32 ERs ERd L 10 MOV L ERs ERd L 4 MOV L aa 16 ERd L 6 MOV L aa 32 ERd L 8 d 16 ERs Rd16 0 3 d 32 ERs Rd16 0 5 ERs Rd16 ERs32 2 ERs32 0 3 aa 16 Rd16 0 3 aa 32 Rd16 0 4 Rs16 ERd 0 2 Rs16 d 16 ERd 0 3 Rs16 d 32 ERd 0 5 ERd32 2 ERd32 Rs16 ERd 0 3 Rs16 aa 16 0 3 Rs16 aa 32 0 4 xx 32 ERd32 0 3 ERs32 ERd32 0 1 ERs ERd32 0 4 d 16 ERs ERd32 ...

Page 935: ...SP ERm ERn L 4 STM ERm ERn SP L 4 MOVFPE aa 16 Rd MOVTPE Rs aa 16 ERs32 ERd 0 4 ERs32 d 16 ERd 0 5 ERs32 d 32 ERd 0 7 ERd32 4 ERd32 ERs32 ERd 0 5 ERs32 aa 16 0 5 ERs32 aa 32 0 6 SP Rn16 SP 2 SP 0 3 SP ERn32 SP 4 SP 0 5 SP 2 SP Rn16 SP 0 3 SP 4 SP ERn32 SP 0 5 SP ERn32 SP 4 SP 7 9 11 1 Repeated for each register restored SP 4 SP ERn32 SP 7 9 11 1 Repeated for each register saved 2 2 Operation Condi...

Page 936: ...ADDS 4 ERd L 2 INC B Rd B 2 INC W 1 Rd W 2 INC W 2 Rd W 2 INC L 1 ERd L 2 INC L 2 ERd L 2 DAA Rd B 2 SUB B Rs Rd B 2 SUB W xx 16 Rd W 4 Rd8 xx 8 Rd8 1 Rd8 Rs8 Rd8 1 Rd16 xx 16 Rd16 3 2 Rd16 Rs16 Rd16 3 1 ERd32 xx 32 ERd32 4 3 ERd32 ERs32 ERd32 4 1 Rd8 xx 8 C Rd8 5 1 Rd8 Rs8 C Rd8 5 1 ERd32 1 ERd32 1 ERd32 2 ERd32 1 ERd32 4 ERd32 1 Rd8 1 Rd8 1 Rd16 1 Rd16 1 Rd16 2 Rd16 1 ERd32 1 ERd32 1 ERd32 2 ERd...

Page 937: ...S Rd B 2 MULXU B Rs Rd B 2 MULXU W Rs ERd W 2 MULXS B Rs Rd B 4 MULXS W Rs ERd W 4 Rd16 Rs16 Rd16 3 1 ERd32 xx 32 ERd32 4 3 ERd32 ERs32 ERd32 4 1 Rd8 xx 8 C Rd8 5 1 Rd8 Rs8 C Rd8 5 1 ERd32 1 ERd32 1 ERd32 2 ERd32 1 ERd32 4 ERd32 1 Rd8 1 Rd8 1 Rd16 1 Rd16 1 Rd16 2 Rd16 1 ERd32 1 ERd32 1 ERd32 2 ERd32 1 Rd8 decimal adjust Rd8 1 Rd8 Rs8 Rd16 unsigned multiplication 3 Rd16 Rs16 ERd32 4 unsigned multip...

Page 938: ...ERd L 2 EXTU W Rd W 2 EXTU L ERd L 2 Rd16 Rs8 Rd16 RdH remainder 6 7 12 RdL quotient unsigned division ERd32 Rs16 ERd32 Ed remainder 6 7 20 Rd quotient unsigned division Rd16 Rs8 Rd16 RdH remainder 8 7 13 RdL quotient signed division ERd32 Rs16 ERd32 Ed remainder 8 7 21 Rd quotient signed division Rd8 xx 8 1 Rd8 Rs8 1 Rd16 xx 16 3 2 Rd16 Rs16 3 1 ERd32 xx 32 4 3 ERd32 ERs32 4 1 0 Rd8 Rd8 1 0 Rd16 ...

Page 939: ...AC LDMAC ERs MACH LDMAC ERs MACL STMAC MACH ERd STMAC MACL ERd bit 7 of Rd16 0 1 bit 15 to 8 of Rd16 bit 15 of ERd32 0 1 bit 31 to 16 of ERd32 ERd 0 CCR set 1 0 4 bit 7 of ERd ERnx ERm MAC MAC 4 signal multiplication 11 11 11 ERn 2 ERn ERm 2 ERm 0 MACH MACL 2 12 ERs MACH 2 12 ERs MACL 2 12 MACH ERd 1 12 MACL ERd 1 12 Operation Condition Code I H N Z V C Advanced No of States 1 L L L L 2 2 2 2 2 ...

Page 940: ...Rs Rd B 2 XOR W xx 16 Rd W 4 XOR W Rs Rd W 2 XOR L xx 32 ERd L 6 XOR L ERs ERd L 4 NOT B Rd B 2 NOT W Rd W 2 NOT L ERd L 2 Rd8 xx 8 Rd8 0 1 Rd8 Rs8 Rd8 0 1 Rd16 xx 16 Rd16 0 2 Rd16 Rs16 Rd16 0 1 ERd32 xx 32 ERd32 0 3 ERd32 ERs32 ERd32 0 2 Rd8 xx 8 Rd8 0 1 Rd8 Rs8 Rd8 0 1 Rd16 xx 16 Rd16 0 2 Rd16 Rs16 Rd16 0 1 ERd32 xx 32 ERd32 0 3 ERd32 ERs32 ERd32 0 2 Rd8 xx 8 Rd8 0 1 Rd8 Rs8 Rd8 0 1 Rd16 xx 16 R...

Page 941: ...HAL W 2 Rd W 2 SHAL L ERd L 2 SHAL L 2 ERd L 2 SHAR B Rd B 2 SHAR B 2 Rd B 2 SHAR W Rd W 2 SHAR W 2 Rd W 2 SHAR L ERd L 2 SHAR L 2 ERd L 2 SHLL B Rd B 2 SHLL B 2 Rd B 2 SHLL W Rd W 2 SHLL W 2 Rd W 2 SHLL L ERd L 2 SHLL L 2 ERd L 2 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operation Condition Code I H N Z V C Advanced No of States 1 C MSB LSB MSB LSB 0 C MSB LSB C 0 ...

Page 942: ... 2 SHLR L 2 ERd L 2 ROTXL B Rd B 2 ROTXL B 2 Rd B 2 ROTXL W Rd W 2 ROTXL W 2 Rd W 2 ROTXL L ERd L 2 ROTXL L 2 ERd L 2 ROTXR B Rd B 2 ROTXR B 2 Rd B 2 ROTXR W Rd W 2 ROTXR W 2 Rd W 2 ROTXR L ERd L 2 ROTXR L 2 ERd L 2 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Operation Condition Code I H N Z V C Advanced No of States 1 C MSB LSB 0 C MSB LSB C MSB LSB ...

Page 943: ...n ERn d ERn ERn ERn aa d PC aa Mnemonic ROTL ROTR ROTL B Rd B 2 ROTL B 2 Rd B 2 ROTL W Rd W 2 ROTL W 2 Rd W 2 ROTL L ERd L 2 ROTL L 2 ERd L 2 ROTR B Rd B 2 ROTR B 2 Rd B 2 ROTR W Rd W 2 ROTR W 2 Rd W 2 ROTR L ERd L 2 ROTR L 2 ERd L 2 Operation Condition Code I H N Z V C Advanced No of States 1 C MSB LSB C MSB LSB ...

Page 944: ...xx 3 Rd B 2 BCLR xx 3 ERd B 4 BCLR xx 3 aa 8 B 4 BCLR xx 3 aa 16 B 6 BCLR xx 3 aa 32 B 8 BCLR Rn Rd B 2 BCLR Rn ERd B 4 BCLR Rn aa 8 B 4 BCLR Rn aa 16 B 6 xx 3 of Rd8 1 1 xx 3 of ERd 1 4 xx 3 of aa 8 1 4 xx 3 of aa 16 1 5 xx 3 of aa 32 1 6 Rn8 of Rd8 1 1 Rn8 of ERd 1 4 Rn8 of aa 8 1 4 Rn8 of aa 16 1 5 Rn8 of aa 32 1 6 xx 3 of Rd8 0 1 xx 3 of ERd 0 4 xx 3 of aa 8 0 4 xx 3 of aa 16 0 5 xx 3 of aa 32...

Page 945: ...Rn aa 32 B 8 BTST xx 3 Rd B 2 BTST xx 3 ERd B 4 BTST xx 3 aa 8 B 4 BTST xx 3 aa 16 B 6 Rn8 of aa 32 0 6 xx 3 of Rd8 xx 3 of Rd8 1 xx 3 of ERd 4 xx 3 of ERd xx 3 of aa 8 4 xx 3 of aa 8 xx 3 of aa 16 5 xx 3 of aa 16 xx 3 of aa 32 6 xx 3 of aa 32 Rn8 of Rd8 Rn8 of Rd8 1 Rn8 of ERd Rn8 of ERd 4 Rn8 of aa 8 Rn8 of aa 8 4 Rn8 of aa 16 5 Rn8 of aa 16 Rn8 of aa 32 6 Rn8 of aa 32 xx 3 of Rd8 Z 1 xx 3 of ER...

Page 946: ... xx 3 Rd B 2 BILD xx 3 ERd B 4 BILD xx 3 aa 8 B 4 BILD xx 3 aa 16 B 6 BILD xx 3 aa 32 B 8 BST xx 3 Rd B 2 BST xx 3 ERd B 4 BST xx 3 aa 8 B 4 xx 3 of aa 32 Z 5 Rn8 of Rd8 Z 1 Rn8 of ERd Z 3 Rn8 of aa 8 Z 3 Rn8 of aa 16 Z 4 Rn8 of aa 32 Z 5 xx 3 of Rd8 C 1 xx 3 of ERd C 3 xx 3 of aa 8 C 3 xx 3 of aa 16 C 4 xx 3 of aa 32 C 5 xx 3 of Rd8 C 1 xx 3 of ERd C 3 xx 3 of aa 8 C 3 xx 3 of aa 16 C 4 xx 3 of a...

Page 947: ...32 B 8 BIAND xx 3 Rd B 2 BIAND xx 3 ERd B 4 BIAND xx 3 aa 8 B 4 BIAND xx 3 aa 16 B 6 BIAND xx 3 aa 32 B 8 BOR xx 3 Rd B 2 BOR xx 3 ERd B 4 C xx 3 of aa 16 5 C xx 3 of aa 32 6 C xx 3 of Rd8 1 C xx 3 of ERd 4 C xx 3 of aa 8 4 C xx 3 of aa 16 5 C xx 3 of aa 32 6 C xx 3 of Rd8 C 1 C xx 3 of ERd C 3 C xx 3 of aa 8 C 3 C xx 3 of aa 16 C 4 C xx 3 of aa 32 C 5 C xx 3 of Rd8 C 1 C xx 3 of ERd C 3 C xx 3 of...

Page 948: ...3 aa 16 B 6 BXOR xx 3 aa 32 B 8 BIXOR xx 3 Rd B 2 BIXOR xx 3 ERd B 4 BIXOR xx 3 aa 8 B 4 BIXOR xx 3 aa 16 B 6 BIXOR xx 3 aa 32 B 8 C xx 3 of aa 8 C 3 C xx 3 of aa 16 C 4 C xx 3 of aa 32 C 5 C xx 3 of Rd8 C 1 C xx 3 of ERd C 3 C xx 3 of aa 8 C 3 C xx 3 of aa 16 C 4 C xx 3 of aa 32 C 5 C xx 3 of Rd8 C 1 C xx 3 of ERd C 3 C xx 3 of aa 8 C 3 C xx 3 of aa 16 C 4 C xx 3 of aa 32 C 5 C xx 3 of Rd8 C 1 C ...

Page 949: ... Z 1 2 3 V 0 2 3 Operation Condition Code Branching Condition I H N Z V C Advanced No of States 1 BRA d 8 BT d 8 2 if condition is true then BRA d 16 BT d 16 4 PC PC d BRN d 8 BF d 8 2 else next BRN d 16 BF d 16 4 BHI d 8 2 BHI d 16 4 BLS d 8 2 BLS d 16 4 BCC d B BHS d 8 2 BCC d 16 BHS d 16 4 BCS d 8 BLO d 8 2 BCS d 16 BLO d 16 4 BNE d 8 2 BNE d 16 4 BEQ d 8 2 BEQ d 16 4 BVC d 8 2 BVC d 16 4 ...

Page 950: ...c Bcc V 1 2 3 N 0 2 3 N 1 2 3 N V 0 2 3 N V 1 2 3 Z N V 0 2 3 Z N V 1 2 3 Operation Condition Code Branching Condition I H N Z V C Advanced No of States 1 BVS d 8 2 BVS d 16 4 BPL d 8 2 BPL d 16 4 BMI d 8 2 BMI d 16 4 BGE d 8 2 BGE d 16 4 BLT d 8 2 BLT d 16 4 BGT d 8 2 BGT d 16 4 BLE d 8 2 BLE d 16 4 ...

Page 951: ...monic JMP BSR JSR RTS JMP ERn 2 JMP aa 24 4 JMP aa 8 2 BSR d 8 2 BSR d 16 4 JSR ERn 2 JSR aa 24 4 JSR aa 8 2 RTS 2 PC ERn 2 PC aa 24 3 PC aa 8 5 PC SP PC PC d 8 4 PC SP PC PC d 16 5 PC SP PC ERn 4 PC SP PC aa 24 5 PC SP PC aa 8 6 PC SP 5 Operation Condition Code I H N Z V C Advanced No of States 1 ...

Page 952: ... d 32 ERs CCR W 10 LDC d 32 ERs EXR W 10 LDC ERs CCR W 4 LDC ERs EXR W 4 LDC aa 16 CCR W 6 LDC aa 16 EXR W 6 LDC aa 32 CCR W 8 LDC aa 32 EXR W 8 PC SP CCR SP 1 8 9 EXR SP vector PC EXR SP CCR SP 5 9 PC SP Transition to power down state 2 xx 8 CCR 1 xx 8 EXR 2 Rs8 CCR 1 Rs8 EXR 1 ERs CCR 3 ERs EXR 3 d 16 ERs CCR 4 d 16 ERs EXR 4 d 32 ERs CCR 6 d 32 ERs EXR 6 ERs CCR ERs32 2 ERs32 4 ERs EXR ERs32 2 ...

Page 953: ... STC EXR aa 16 W 6 STC CCR aa 32 W 8 STC EXR aa 32 W 8 ANDC xx 8 CCR B 2 ANDC xx 8 EXR B 4 ORC xx 8 CCR B 2 ORC xx 8 EXR B 4 XORC xx 8 CCR B 2 XORC xx 8 EXR B 4 NOP 2 CCR Rd8 1 EXR Rd8 1 CCR ERd 3 EXR ERd 3 CCR d 16 ERd 4 EXR d 16 ERd 4 CCR d 32 ERd 6 EXR d 32 ERd 6 ERd32 2 ERd32 CCR ERd 4 ERd32 2 ERd32 EXR ERd 4 CCR aa 16 4 EXR aa 16 4 CCR aa 32 5 EXR aa 32 5 CCR xx 8 CCR 1 EXR xx 8 EXR 2 CCR xx ...

Page 954: ...in the H8S 2633 Series 3 Set to 1 when a carry or borrow occurs at bit 11 otherwise cleared to 0 4 Set to 1 when a carry or borrow occurs at bit 27 otherwise cleared to 0 5 Retains its previous value when the result is zero otherwise cleared to 0 6 Set to 1 when the divisor is negative otherwise cleared to 0 7 Set to 1 when the divisor is zero otherwise cleared to 0 8 Set to 1 when the quotient is...

Page 955: ...943 A 2 Instruction Codes Table A 2 shows the instruction codes ...

Page 956: ...16 BF d 16 Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion ADD ADDS ADDX AND ANDC BAND Bcc B B W W L L L L L B B B B W W L L B B B B B B B 1 0 0 ers IMM erd 0 0 0 0 0 0 erd erd erd erd erd erd ers IMM IMM 0 erd 0 IMM 0 IMM 0 0 0 8 0 7 0 7 0 0 0 0 9 0 E 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 rd 8 9 9 A A B B B rd E rd...

Page 957: ...E d 8 BLE d 16 Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion Bcc 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 A 8 B 8 C 8 D 8 E 8 F 8 2 3 4 5 6 7 8 9 A B C D E F disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp...

Page 958: ...byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion BCLR BIAND BILD BIOR B B B B B B B B B B B B B B B B B B B B B B B B B 0 0 0 1 0 1 0 1 0 IMM erd erd IMM erd IMM erd IMM erd 0 1 1 1 IMM IMM IMM IMM 0 1 1 1 IMM IMM IMM IMM 7 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 2 D F A A 2 D F A A 6 C E A A 7 C E A A 4 C E A A 1 3 rn 1 3 1 3 1 3 1 3 rd 0 8 8 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0...

Page 959: ...te 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion BIST BIXOR BLD BNOT B B B B B B B B B B B B B B B B B B B B B B B B B 1 0 1 0 0 0 0 0 0 IMM erd IMM erd IMM erd IMM erd erd IMM IMM IMM IMM IMM IMM IMM IMM 1 1 0 0 IMM IMM IMM IMM 1 1 0 0 IMM IMM IMM IMM 1 1 1 1 0 0 0 0 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 7 D F A A 5 C E A A 7 C E A A 1 D F A A 1 D F A A 1 3 1 3 1 3 1 3 rn...

Page 960: ... byte 8th byte 9th byte 10th byte Instruc tion BOR BSET BSR BST BTST B B B B B B B B B B B B B B B B B B B B B B B B B B B 0 0 0 0 0 0 0 0 0 0 IMM erd IMM erd erd IMM erd IMM erd erd abs abs abs disp abs abs IMM IMM IMM IMM IMM IMM IMM IMM 0 0 0 0 IMM IMM IMM IMM 0 0 0 0 IMM IMM IMM IMM 0 0 0 0 0 0 0 0 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 4 C E A A 0 D F A A 0 D F A A 5 C 7 D ...

Page 961: ...te 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion BTST BXOR CLRMAC CMP DAA DAS DEC DIVXS DIVXU EEPMOV B B B B B B B B B B W W L L B B B W W L L B W B W 0 0 1 IMM erd ers 0 0 0 0 0 erd erd erd erd erd IMM IMM 0 erd 0 IMM 0 IMM 0 0 7 6 6 7 7 7 6 6 A 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 E A A 5 C E A A rd C 9 D A F F F A B B B B 1 1 1 3 B B 1 3 1 3 rs 2 rs 2 0 0 0 5 D 7 F...

Page 962: ...nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion EXTS EXTU INC JMP JSR LDC W L W L B W W L L B B B B W W W W W W W W W W 0 0 ern ern 0 0 0 0 erd erd erd erd ers ers ers ers ers ers ers ers 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 7 7 7 A B B B B 9 A B D E F 7 1 3 3 1 1 1 1 1 1 1 1 1 1 D F 5 7 0 5 D 7 F 4 0 1 4 4 4 4 4 ...

Page 963: ...s Rd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion LDC LDM LDMAC MAC MOV W W L L L L L B B B B B B B B B B B B B B B B W W W W W 0 0 0 0 1 1 0 1 0 0 0 ers ers ers ers erd erd erd erd ers ers ers 0 0 0 ern 1 ern 2 ern 3 0 0 0 0 0 F 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 6 7 1 1 1 1 1 rd C 8 E 8 C rd A A 8 E 8 C ...

Page 964: ...th byte 7th byte 8th byte 9th byte 10th byte Instruc tion MOV MOVFPE MOVTPE MULXS MULXU W W W W W W W W W L L L L L L L L L L L L L L B B B W B W 0 1 1 0 1 1 ers erd erd erd erd ers 0 0 0 erd erd erd ers ers ers ers erd erd erd erd 0 0 0 0 0 0 0 0 0 0 0 erd erd erd erd erd ers ers ers ers ers erd 0 0 erd ers 0 0 0 0 1 1 0 1 6 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 5 D B B 9 F 8 D B B A ...

Page 965: ...struction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion NEG NOP NOT OR ORC POP PUSH ROTL B W L B W L B B W W L L B B W L W L B B W W L L 0 0 0 0 0 erd erd erd erd erd 1 1 1 0 1 1 1 C 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 7 7 7 0 7 7 7 rd 4 9 4 A 1 4 1 D 1 D 1 2 2 2 2 2 2 8 9 B 0 0 1 3 rs 4 rs 4 F 4 7 0 F 0 8 C 9 D B F rd rd 0 rd rd rd rd...

Page 966: ... SHAL L 2 ERd Mnemonic Size Instruction Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion ROTR ROTXL ROTXR RTE RTS SHAL B B W W L L B B W W L L B B W W L L B B W W L L 0 0 0 0 0 0 0 0 erd erd erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 3 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 8 C 9 D B F 0 4 1 5...

Page 967: ...on Format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion SHAR SHLL SHLR SLEEP STC B B W W L L B B W W L L B B W W L L B B W W W W W W W W 0 0 0 0 0 0 erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 8 C 9 D B F 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4...

Page 968: ...t 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte Instruc tion STC STM STMAC SUB SUBS SUBX TAS 2 TRAPA XOR W W W W L L L L L B W W L L L L L B B B B B W W L L 1 00 ers IMM 0 0 0 0 0 0 erd erd erd erd erd erd erd ers 0 0 0 0 ern ern ern erd 0 0 0 0 0 0 0 0 0 1 7 1 7 1 1 1 1 B 1 0 5 D 1 7 6 7 0 1 1 1 1 1 1 1 8 9 9 A A B B B rd E 1 7 rd 5 9 5 A 1 4 4 4 4 1 2...

Page 969: ...gister Register Field General Register 000 001 111 ER0 ER1 ER7 0000 0001 0111 1000 1001 1111 R0 R1 R7 E0 E1 E7 0000 0001 0111 1000 1001 1111 R0H R1H R7H R0L R1L R7L 16 Bit Register 8 Bit Register IMM abs disp rs rd rn ers erd ern erm The register fields specify general registers as follows Immediate data 2 3 8 16 or 32 bits Absolute address 8 16 24 or 32 bits Displacement 8 16 or 32 bits Register ...

Page 970: ... 3 BLS DIVXU BTST STC STMAC LDC LDMAC 4 ORC OR BCC RTS OR BOR BIOR 6 ANDC AND BNE RTE AND 5 XORC XOR BCS BSR XOR BXOR BIXOR BAND BIAND 7 LDC BEQ TRAPA BST BIST BLD BILD 8 BVC MOV 9 BVS A BPL JMP B BMI EEPMOV C BGE BSR D BLT MOV E ADDX SUBX BGT JSR F BLE MOV B ADD ADDX CMP SUBX OR XOR AND MOV ADD SUB MOV MOV CMP Table A 3 2 Table A 3 2 Table A 3 2 Table A 3 2 Table A 3 2 Table A 3 2 Table A 3 2 Tab...

Page 971: ...R BCC MOVFPE OR OR 5 INC EXTU DEC BCS XOR XOR 6 MAC BNE AND AND 7 INC SHLL SHLR ROTXL ROTXR EXTU DEC BEQ LDC STC 8 SLEEP BVC MOV ADDS SHAL SHAR ROTL ROTR NEG SUBS 9 BVS A CLRMAC BPL MOV B NEG BMI ADD MOV SUB CMP C SHAL SHAR ROTL ROTR BGE MOVTPE D INC EXTS DEC BLT E TAS BGT F INC SHAL SHAR ROTL ROTR EXTS DEC BLE BH AH AL Table A 3 3 Table A 3 3 Table A 3 3 Table A 3 4 Table A 3 4 Table A 3 Operatio...

Page 972: ...when most significant bit of DH is 1 Notes AH AL BH BL CH CL 01C05 01D05 01F06 7Cr06 1 7Cr07 1 7Dr06 1 7Dr07 1 7Eaa6 2 7Eaa7 2 7Faa6 2 7Faa7 2 0 MULXS BSET BSET BSET BSET 1 DIVXS BNOT BNOT BNOT BNOT 2 MULXS BCLR BCLR BCLR BCLR 3 DIVXS BTST BTST BTST BTST 4 OR 5 XOR 6 AND 7 8 9 A B C D E F 1 2 BOR BIOR BXOR BIXOR BAND BIAND BLD BILD BST BIST BOR BIOR BXOR BIXOR BAND BIAND BLD BILD BST BIST Table A ...

Page 973: ... is 0 Instruction when most significant bit of HH is 1 Note aa is the absolute address specification 5th byte 6th byte EH EL FH FL 7th byte 8th byte GH GL HH HL 6A10aaaa6 6A10aaaa7 6A18aaaa6 6A18aaaa7 AHALBHBLCHCLDHDLEH EL 0 BSET 1 BNOT 2 BCLR 3 BTST BOR BIOR BXOR BIXOR BAND BIAND BLD BILD BST BIST 4 5 6 7 8 9 A B C D E F 6A30aaaaaaaa6 6A30aaaaaaaa7 6A38aaaaaaaa6 6A38aaaaaaaa7 AHALBHBL FHFLGH GL 0...

Page 974: ...ecution of an instruction can be calculated from these two tables as follows Execution states I SI J SJ K SK L SL M SM N SN Examples Advanced mode program code and stack located in external memory on chip supporting modules accessed in two states with 8 bit bus width external devices accessed in three states with one wait state and 16 bit bus width 1 BSET 0 FFFFC7 8 From table A 5 I L 2 J K M N 0 ...

Page 975: ...hip Memory 8 Bit Bus 16 Bit Bus 2 State Access 3 State Access 2 State Access 3 State Access Instruction fetch SI 1 4 2 4 6 2m 2 3 m Branch address read SJ Stack operation SK Byte data access SL 2 2 3 m Word data access SM 4 4 6 2m Internal operation SN 1 1 1 1 1 1 1 Legend m Number of wait states inserted into external device access ...

Page 976: ...DD L xx 32 ERd 3 ADD L ERs ERd 1 ADDS ADDS 1 2 4 ERd 1 ADDX ADDX xx 8 Rd 1 ADDX Rs Rd 1 AND AND B xx 8 Rd 1 AND B Rs Rd 1 AND W xx 16 Rd 2 AND W Rs Rd 1 AND L xx 32 ERd 3 AND L ERs ERd 2 ANDC ANDC xx 8 CCR 1 ANDC xx 8 EXR 2 BAND BAND xx 3 Rd 1 BAND xx 3 ERd 2 1 BAND xx 3 aa 8 2 1 BAND xx 3 aa 16 3 1 BAND xx 3 aa 32 4 1 Bcc BRA d 8 BT d 8 2 BRN d 8 BF d 8 2 BHI d 8 2 BLS d 8 2 BCC d 8 BHS d 8 2 BCS...

Page 977: ...T d 16 2 1 BRN d 16 BF d 16 2 1 BHI d 16 2 1 BLS d 16 2 1 BCC d 16 BHS d 16 2 1 BCS d 16 BLO d 16 2 1 BNE d 16 2 1 BEQ d 16 2 1 BVC d 16 2 1 BVS d 16 2 1 BPL d 16 2 1 BMI d 16 2 1 BGE d 16 2 1 BLT d 16 2 1 BGT d 16 2 1 BLE d 16 2 1 BCLR BCLR xx 3 Rd 1 BCLR xx 3 ERd 2 2 BCLR xx 3 aa 8 2 2 BCLR xx 3 aa 16 3 2 BCLR xx 3 aa 32 4 2 BCLR Rn Rd 1 BCLR Rn ERd 2 2 BCLR Rn aa 8 2 2 BCLR Rn aa 16 3 2 BCLR Rn...

Page 978: ...1 BILD xx 3 ERd 2 1 BILD xx 3 aa 8 2 1 BILD xx 3 aa 16 3 1 BILD xx 3 aa 32 4 1 BIOR BIOR xx 8 Rd 1 BIOR xx 8 ERd 2 1 BIOR xx 8 aa 8 2 1 BIOR xx 8 aa 16 3 1 BIOR xx 8 aa 32 4 1 BIST BIST xx 3 Rd 1 BIST xx 3 ERd 2 2 BIST xx 3 aa 8 2 2 BIST xx 3 aa 16 3 2 BIST xx 3 aa 32 4 2 BIXOR BIXOR xx 3 Rd 1 BIXOR xx 3 ERd 2 1 BIXOR xx 3 aa 8 2 1 BIXOR xx 3 aa 16 3 1 BIXOR xx 3 aa 32 4 1 BLD BLD xx 3 Rd 1 BLD xx...

Page 979: ...OT Rn ERd 2 2 BNOT Rn aa 8 2 2 BNOT Rn aa 16 3 2 BNOT Rn aa 32 4 2 BOR BOR xx 3 Rd 1 BOR xx 3 ERd 2 1 BOR xx 3 aa 8 2 1 BOR xx 3 aa 16 3 1 BOR xx 3 aa 32 4 1 BSET BSET xx 3 Rd 1 BSET xx 3 ERd 2 2 BSET xx 3 aa 8 2 2 BSET xx 3 aa 16 3 2 BSET xx 3 aa 32 4 2 BSET Rn Rd 1 BSET Rn ERd 2 2 BSET Rn aa 8 2 2 BSET Rn aa 16 3 2 BSET Rn aa 32 4 2 BSR BSR d 8 2 2 BSR d 16 2 2 1 BST BST xx 3 Rd 1 BST xx 3 ERd 2...

Page 980: ...Rd 1 BTST Rn ERd 2 1 BTST Rn aa 8 2 1 BTST Rn aa 16 3 1 BTST Rn aa 32 4 1 BXOR BXOR xx 3 Rd 1 BXOR xx 3 ERd 2 1 BXOR xx 3 aa 8 2 1 BXOR xx 3 aa 16 3 1 BXOR xx 3 aa 32 4 1 CLRMAC CLRMAC 1 1 3 CMP CMP B xx 8 Rd 1 CMP B Rs Rd 1 CMP W xx 16 Rd 2 CMP W Rs Rd 1 CMP L xx 32 ERd 3 CMP L ERs ERd 1 DAA DAA Rd 1 DAS DAS Rd 1 DEC DEC B Rd 1 DEC W 1 2 Rd 1 DEC L 1 2 ERd 1 DIVXS DIVXS B Rs Rd 2 11 DIVXS W Rs ER...

Page 981: ...1 EXTU L ERd 1 INC INC B Rd 1 INC W 1 2 Rd 1 INC L 1 2 ERd 1 JMP JMP ERn 2 JMP aa 24 2 1 JMP aa 8 2 2 1 JSR JSR ERn 2 2 JSR aa 24 2 2 1 JSR aa 8 2 2 2 LDC LDC xx 8 CCR 1 LDC xx 8 EXR 2 LDC Rs CCR 1 LDC Rs EXR 1 LDC ERs CCR 2 1 LDC ERs EXR 2 1 LDC d 16 ERs CCR 3 1 LDC d 16 ERs EXR 3 1 LDC d 32 ERs CCR 5 1 LDC d 32 ERs EXR 5 1 LDC ERs CCR 2 1 1 LDC ERs EXR 2 1 1 LDC aa 16 CCR 3 1 LDC aa 16 EXR 3 1 L...

Page 982: ...Rn ERm 2 2 MOV MOV B xx 8 Rd 1 MOV B Rs Rd 1 MOV B ERs Rd 1 1 MOV B d 16 ERs Rd 2 1 MOV B d 32 ERs Rd 4 1 MOV B ERs Rd 1 1 1 MOV B aa 8 Rd 1 1 MOV B aa 16 Rd 2 1 MOV B aa 32 Rd 3 1 MOV B Rs ERd 1 1 MOV B Rs d 16 ERd 2 1 MOV B Rs d 32 ERd 4 1 MOV B Rs ERd 1 1 1 MOV B Rs aa 8 1 1 MOV B Rs aa 16 2 1 MOV B Rs aa 32 3 1 MOV W xx 16 Rd 2 MOV W Rs Rd 1 MOV W ERs Rd 1 1 MOV W d 16 ERs Rd 2 1 MOV W d 32 ER...

Page 983: ...2 2 MOV L d 16 ERs ERd 3 2 MOV L d 32 ERs ERd 5 2 MOV L ERs ERd 2 2 1 MOV L aa 16 ERd 3 2 MOV L aa 32 ERd 4 2 MOV L ERs ERd 2 2 MOV L ERs d 16 ERd 3 2 MOV L ERs d 32 ERd 5 2 MOV L ERs ERd 2 2 1 MOV L ERs aa 16 3 2 MOV L ERs aa 32 4 2 MOVFPE MOVFPE aa 16 Rd Can not be used in the H8S 2633 Series MOVTPE MOVTPE Rs aa 16 MULXS MULXS B Rs Rd 2 2 3 MULXS W Rs ERd 2 3 3 MULXU MULXU B Rs Rd 1 2 3 MULXU W ...

Page 984: ... 1 OR L xx 32 ERd 3 OR L ERs ERd 2 ORC ORC xx 8 CCR 1 ORC xx 8 EXR 2 POP POP W Rn 1 1 1 POP L ERn 2 2 1 PUSH PUSH W Rn 1 1 1 PUSH L ERn 2 2 1 ROTL ROTL B Rd 1 ROTL B 2 Rd 1 ROTL W Rd 1 ROTL W 2 Rd 1 ROTL L ERd 1 ROTL L 2 ERd 1 ROTR ROTR B Rd 1 ROTR B 2 Rd 1 ROTR W Rd 1 ROTR W 2 Rd 1 ROTR L ERd 1 ROTR L 2 ERd 1 ROTXL ROTXL B Rd 1 ROTXL B 2 Rd 1 ROTXL W Rd 1 ROTXL W 2 Rd 1 ROTXL L ERd 1 ROTXL L 2 ER...

Page 985: ... L ERd 1 ROTXR L 2 ERd 1 RTE RTE 2 2 3 1 1 RTS RTS 2 2 1 SHAL SHAL B Rd 1 SHAL B 2 Rd 1 SHAL W Rd 1 SHAL W 2 Rd 1 SHAL L ERd 1 SHAL L 2 ERd 1 SHAR SHAR B Rd 1 SHAR B 2 Rd 1 SHAR W Rd 1 SHAR W 2 Rd 1 SHAR L ERd 1 SHAR L 2 ERd 1 SHLL SHLL B Rd 1 SHLL B 2 Rd 1 SHLL W Rd 1 SHLL W 2 Rd 1 SHLL L ERd 1 SHLL L 2 ERd 1 SHLR SHLR B Rd 1 SHLR B 2 Rd 1 SHLR W Rd 1 SHLR W 2 Rd 1 SHLR L ERd 1 SHLR L 2 ERd 1 SLE...

Page 986: ... CCR d 32 ERd 5 1 STC W EXR d 32 ERd 5 1 STC W CCR ERd 2 1 1 STC W EXR ERd 2 1 1 STC W CCR aa 16 3 1 STC W EXR aa 16 3 1 STC W CCR aa 32 4 1 STC W EXR aa 32 4 1 STM STM L ERn ERn 1 SP 2 4 1 STM L ERn ERn 2 SP 2 6 1 STM L ERn ERn 3 SP 2 8 1 STMAC STMAC MACH ERd 1 3 STMAC MACL ERd 1 3 SUB SUB B Rs Rd 1 SUB W xx 16 Rd 2 SUB W Rs Rd 1 SUB L xx 32 ERd 3 SUB L ERs ERd 1 SUBS SUBS 1 2 4 ERd 1 SUBX SUBX x...

Page 987: ...R W xx 16 Rd 2 XOR W Rs Rd 1 XOR L xx 32 ERd 3 XOR L ERs ERd 2 XORC XORC xx 8 CCR 1 XORC xx 8 EXR 2 Notes 1 2 when EXR is invalid 3 when EXR is valid 2 When n bytes of data are transferred 3 An internal operation may require between 0 and 3 additional states depending on the preceding instruction 4 This instruction should be used with the ER0 ER1 ER4 or ER5 general register only ...

Page 988: ... of execution Read effective address word size read No read or write Read 2nd word of current instruction word size read Legend R B Byte size read R W Word size read W B Byte size write W W Word size write M Transfer of the bus is not performed immediately after this cycle 2nd Address of 2nd word 3rd and 4th bytes 3rd Address of 3rd word 5th and 6th bytes 4th Address of 4th word 7th and 8th bytes ...

Page 989: ...ree state access with no wait states ø Address bus RD HWR LWR R W 2nd Fetching 2nd byte of instruction at jump address Fetching 1nd byte of instruction at jump address Fetching 4th byte of instruction Fetching 3rd byte of instruction R W EA High level Internal operation Figure A 1 Address Bus RD HWR and LWR Timing 8 Bit Bus Three State Access No Wait States ...

Page 990: ...NEXT BAND xx 3 Rd R W NEXT BAND xx 3 ERd R W 2nd R B EA R W M NEXT BAND xx 3 aa 8 R W 2nd R B EA R W M NEXT BAND xx 3 aa 16 R W 2nd R W 3rd R B EA R W M NEXT BAND xx 3 aa 32 R W 2nd R W 3rd R W 4th R B EA R W M NEXT BRA d 8 BT d 8 R W NEXT R W EA BRN d 8 BF d 8 R W NEXT R W EA BHI d 8 R W NEXT R W EA BLS d 8 R W NEXT R W EA BCC d 8 BHS d 8 R W NEXT R W EA BCS d 8 BLO d 8 R W NEXT R W EA BNE d 8 R ...

Page 991: ... 2nd Internal operation R W EA 1 state BVC d 16 R W 2nd Internal operation R W EA 1 state BVS d 16 R W 2nd Internal operation R W EA 1 state BPL d 16 R W 2nd Internal operation R W EA 1 state BMI d 16 R W 2nd Internal operation R W EA 1 state BGE d 16 R W 2nd Internal operation R W EA 1 state BLT d 16 R W 2nd Internal operation R W EA 1 state BGT d 16 R W 2nd Internal operation R W EA 1 state BLE ...

Page 992: ... EA R W M NEXT BIOR xx 3 Rd R W NEXT BIOR xx 3 ERd R W 2nd R B EA R W M NEXT BIOR xx 3 aa 8 R W 2nd R B EA R W M NEXT BIOR xx 3 aa 16 R W 2nd R W 3rd R B EA R W M NEXT BIOR xx 3 aa 32 R W 2nd R W 3rd R W 4th R B EA R W M NEXT BIST xx 3 Rd R W NEXT BIST xx 3 ERd R W 2nd R B M EA R W M NEXT W B EA BIST xx 3 aa 8 R W 2nd R B M EA R W M NEXT W B EA BIST xx 3 aa 16 R W 2nd R W 3rd R B M EA R W M NEXT W...

Page 993: ...SET xx 3 ERd R W 2nd R B M EA R W M NEXT W B EA BSET xx 3 aa 8 R W 2nd R B M EA R W M NEXT W B EA BSET xx 3 aa 16 R W 2nd R W 3rd R B M EA R W M NEXT W B EA BSET xx 3 aa 32 R W 2nd R W 3rd R W 4th R B M EA R W M NEXT W B EA BSET Rn Rd R W NEXT BSET Rn ERd R W 2nd R B M EA R W M NEXT W B EA BSET Rn aa 8 R W 2nd R B M EA R W M NEXT W B EA BSET Rn aa 16 R W 2nd R W 3rd R B M EA R W M NEXT W B EA BSET...

Page 994: ...A R W M NEXT CLRMAC R W NEXT Internal operation 1 state CMP B xx 8 Rd R W NEXT CMP B Rs Rd R W NEXT CMP W xx 16 Rd R W 2nd R W NEXT CMP W Rs Rd R W NEXT CMP L xx 32 ERd R W 2nd R W 3rd R W NEXT CMP L ERs ERd R W NEXT DAA Rd R W NEXT DAS Rd R W NEXT DEC B Rd R W NEXT DEC W 1 2 Rd R W NEXT DEC L 1 2 ERd R W NEXT DIVXS B Rs Rd R W 2nd R W NEXT Internal operation 11 states DIVXS W Rs ERd R W 2nd R W N...

Page 995: ...R W 3rd R W NEXT R W EA LDC d 32 ERs CCR R W 2nd R W 3rd R W 4th R W 5th R W NEXT R W EA LDC d 32 ERs EXR R W 2nd R W 3rd R W 4th R W 5th R W NEXT R W EA LDC ERs CCR R W 2nd R W NEXT Internal operation R W EA 1 state LDC ERs EXR R W 2nd R W NEXT Internal operation R W EA 1 state LDC aa 16 CCR R W 2nd R W 3rd R W NEXT R W EA LDC aa 16 EXR R W 2nd R W 3rd R W NEXT R W EA LDC aa 32 CCR R W 2nd R W 3r...

Page 996: ...A MOV B Rs ERd R W NEXT Internal operation W B EA 1 state MOV B Rs aa 8 R W NEXT W B EA MOV B Rs aa 16 R W 2nd R W NEXT W B EA MOV B Rs aa 32 R W 2nd R W 3rd R W NEXT W B EA MOV W xx 16 Rd R W 2nd R W NEXT MOV W Rs Rd R W NEXT MOV W ERs Rd R W NEXT R W EA MOV W d 16 ERs Rd R W 2nd R W NEXT R W EA MOV W d 32 ERs Rd R W 2nd R W 3rd R W 4th R W NEXT R W EA MOV W ERs Rd R W NEXT Internal operation R W...

Page 997: ... 5th R W NEXT W W M EA W W EA 2 MOV L ERs ERd R W 2nd R W M NEXT Internal operation W W M EA W W EA 2 1 state MOV L ERs aa 16 R W 2nd R W M 3rd R W NEXT W W M EA W W EA 2 MOV L ERs aa 32 R W 2nd R W M 3rd R W 4th R W NEXT W W M EA W W EA 2 MOVFPE aa 16 Rd Cannot be used in the H8S 2633 Series MOVTPE Rs aa 16 MULXS B Rs Rd R W 2nd R W NEXT Internal operation 2 states MULXS W Rs ERd R W 2nd R W NEXT...

Page 998: ...Rd R W NEXT ROTR B Rd R W NEXT ROTR B 2 Rd R W NEXT ROTR W Rd R W NEXT ROTR W 2 Rd R W NEXT ROTR L ERd R W NEXT ROTR L 2 ERd R W NEXT ROTXL B Rd R W NEXT ROTXL B 2 Rd R W NEXT ROTXL W Rd R W NEXT ROTXL W 2 Rd R W NEXT ROTXL L ERd R W NEXT ROTXL L 2 ERd R W NEXT ROTXR B Rd R W NEXT ROTXR B 2 Rd R W NEXT ROTXR W Rd R W NEXT ROTXR W 2 Rd R W NEXT ROTXR L ERd R W NEXT ROTXR L 2 ERd R W NEXT RTE R W NE...

Page 999: ... L ERd R W NEXT SHLR L 2 ERd R W NEXT SLEEP R W NEXT Internal operation M STC CCR Rd R W NEXT STC EXR Rd R W NEXT STC CCR ERd R W 2nd R W NEXT W W EA STC EXR ERd R W 2nd R W NEXT W W EA STC CCR d 16 ERd R W 2nd R W 3rd R W NEXT W W EA STC EXR d 16 ERd R W 2nd R W 3rd R W NEXT W W EA STC CCR d 32 ERd R W 2nd R W 3rd R W 4th R W 5th R W NEXT W W EA STC EXR d 32 ERd R W 2nd R W 3rd R W 4th R W 5th R ...

Page 1000: ...MACL ERd R W NEXT SUB B Rs Rd R W NEXT SUB W xx 16 Rd R W 2nd R W NEXT SUB W Rs Rd R W NEXT SUB L xx 32 ERd R W 2nd R W 3rd R W NEXT SUB L ERs ERd R W NEXT SUBS 1 2 4 ERd R W NEXT SUBX xx 8 Rd R W NEXT SUBX Rs Rd R W NEXT TAS ERd 8 R W 2nd R W NEXT R B M EA W B EA TRAPA x 2 R W NEXT Internal operation W W stack L W W stack H W W stack EXR R W M VEC R W VEC 2 Internal operation R W 7 1 state 1 stat...

Page 1001: ...tion of the instruction n is the initial value of R4L or R4 If n 0 these bus cycles are not executed 3 Repeated two times to save or restore two registers three times for three registers or four times for four registers 4 Start address after return 5 Start address of the program 6 Prefetch address equal to two plus the PC value pushed onto the stack In recovery from sleep mode or software standby ...

Page 1002: ...ds 7 for byte operands Si Di Ri Dn 0 1 Z C The i th bit of the source operand The i th bit of the destination operand The i th bit of the result The specified bit in the destination operand Not affected Modified according to the result of the instruction see definition Always cleared to 0 Always set to 1 Undetermined no guaranteed value Z flag before instruction execution C flag before instruction...

Page 1003: ...m Rm ADDS ADDX H Sm 4 Dm 4 Dm 4 Rm 4 Sm 4 Rm 4 N Rm Z Z Rm R0 V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm AND 0 N Rm Z Rm Rm 1 R0 ANDC Stores the corresponding bits of the result No flags change when the operand is EXR BAND C C Dn Bcc BCLR BIAND C C Dn BILD C Dn BIOR C C Dn BIST BIXOR C C Dn C Dn BLD C Dn BNOT BOR C C Dn BSET BSR BST BTST Z Dn BXOR C C Dn C Dn CLRMAC ...

Page 1004: ... decimal arithmetic carry DAS N Rm Z Rm Rm 1 R0 C decimal arithmetic borrow DEC N Rm Z Rm Rm 1 R0 V Dm Rm DIVXS N Sm Dm Sm Dm Z Sm Sm 1 S0 DIVXU N Sm Z Sm Sm 1 S0 EEPMOV EXTS 0 N Rm Z Rm Rm 1 R0 EXTU 0 0 Z Rm Rm 1 R0 INC N Rm Z Rm Rm 1 R0 V Dm Rm JMP JSR LDC Stores the corresponding bits of the result No flags change when the operand is EXR LDM LDMAC MAC ...

Page 1005: ...4 Rm 4 N Rm Z Rm Rm 1 R0 V Dm Rm C Dm Rm NOP NOT 0 N Rm Z Rm Rm 1 R0 OR 0 N Rm Z Rm Rm 1 R0 ORC Stores the corresponding bits of the result No flags change when the operand is EXR POP 0 N Rm Z Rm Rm 1 R0 PUSH 0 N Rm Z Rm Rm 1 R0 ROTL 0 N Rm Z Rm Rm 1 R0 C Dm 1 bit shift or C Dm 1 2 bit shift ROTR 0 N Rm Z Rm Rm 1 R0 C D0 1 bit shift or C D1 2 bit shift ...

Page 1006: ...shift V Dm Dm 1 Dm 2 Dm Dm 1 Dm 2 2 bit shift C Dm 1 bit shift or C Dm 1 2 bit shift SHAR 0 N Rm Z Rm Rm 1 R0 C D0 1 bit shift or C D1 2 bit shift SHLL 0 N Rm Z Rm Rm 1 R0 C Dm 1 bit shift or C Dm 1 2 bit shift SHLR 0 0 N Rm Z Rm Rm 1 R0 C D0 1 bit shift or C D1 2 bit shift SLEEP STC STM STMAC N 1 if MAC instruction resulted in negative value in MAC register Z 1 if MAC instruction resulted in zero...

Page 1007: ...Rm SUBS SUBX H Sm 4 Dm 4 Dm 4 Rm 4 Sm 4 Rm 4 N Rm Z Z Rm R0 V Sm Dm Rm Sm Dm Rm C Sm Dm Dm Rm Sm Rm TAS 0 N Dm Z Dm Dm 1 D0 TRAPA XOR 0 N Rm Z Rm Rm 1 R0 XORC Stores the corresponding bits of the result No flags change when the operand is EXR Note This instruction should be used with the ER0 ER1 ER4 or ER5 general register only ...

Page 1008: ...DRBL0 DACNTL0 DA5 DA4 DA3 DA2 DA1 DA0 CFS REGS H FDBC DADRAH1 DACR1 DA13 TEST DA12 PWME DA11 DA10 DA9 OEBDA8 OEADA7 OS DA6 CKS PWM1 8 H FDBD DADRAL1 DA5 DA4 DA3 DA2 DA1 DA0 CFS H FDBE DADRBH1 DACNTH1 DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 H FDBF DADRBL1 DACNTL1 DA5 DA4 DA3 DA2 DA1 DA0 CFS REGS H FDC0 H FDC1 H FDC2 TCR2 TCR3 TCSR2 CMIEB CMIEB CMFB CMIEA CMIEA CMFA OVIE OVIE OVF CCLR1 CCLR1 CCLR0 CCLR0...

Page 1009: ...A0 H FDE9 MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 H FDEA MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0 H FDEB PFCR CSS07 CSS36 BUZZE LCASS AE3 AE2 AE1 AE0 H FDEC LPWRCR DTON LSON NESEL SUBSTP RFCUT STC1 STC0 H FE00 BARA PBC 8 H FE01 BAA23 BAA22 BAA21 BAA20 BAA19 BAA18 BAA17 BAA16 H FE02 BAA15 BAA14 BAA13 BAA12 BAA11 BAA10 BAA9 BAA8 H FE03 BAA7 BAA6 BAA5 BA...

Page 1010: ...R7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 H FE2E NDRH NDR11 NDR10 NDR9 NDR8 H FE2F NDRL NDR3 NDR2 NDR1 NDR0 H FE30 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 8 H FE32 P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR H FE36 P7DDR P77DDR P76DDR P75DDR P74DDR P73DDR P72DDR P71DDR P70DDR H FE39 PADDR PA3DDR PA2DDR PA1DDR PA0DDR H FE3A PBDDR PB7DDR PB6DDR PB5DDR PB4DDR ...

Page 1011: ...3A H FE89 H FE8A TGR3B H FE8B H FE8C TGR3C H FE8D H FE8E TGR3D H FE8F H FE90 TCR4 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU4 16 H FE91 TMDR4 MD3 MD2 MD1 MD0 H FE92 TIOR4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H FE94 TIER4 TTGE TCIEU TCIEV TGIEB TGIEA H FE95 TSR4 TCFD TCFU TCFV TGFB TGFA H FE96 TCNT4 H FE97 H FE98 TGR4A H FE99 H FE9A TGR4B H FE9B H FEA0 TCR5 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1...

Page 1012: ...1 IPR0 H FEC9 IPRJ IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 H FECA IPRK IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 H FECB IPRL IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 H FECE IPRO IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 H FED0 ABWCR ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Bus 8 H FED1 ASTCR AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 controller H FED2 WCRH W71 W70 W61 W60 W51 W50 W41 W40 H FED3 WCRL W31 W30 W21 W20 W11 W10 W01 W00 H FED4 BCRH IC...

Page 1013: ... P37DR P36DR P35DR P34DR P33DR P32DR P31DR P30DR H FF04 H FF05 H FF06 P7DR P77DR P76DR P75DR P74DR P73DR P72DR P71DR P70DR H FF07 H FF09 PADR PA3DR PA2DR PA1DR PA0DR H FF0A PBDR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR H FF0B PCDR PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR H FF0C PDDR PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR H FF0D PEDR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR ...

Page 1014: ...GR0C H FF1D H FF1E TGR0D H FF1F H FF20 TCR1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU1 16 H FF21 TMDR1 MD3 MD2 MD1 MD0 H FF22 TIOR1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H FF24 TIER1 TTGE TCIEU TCIEV TGIEB TGIEA H FF25 TSR1 TCFD TCFU TCFV TGFB TGFA H FF26 TCNT1 H FF27 H FF28 TGR1A H FF29 H FF2A TGR1B H FF2B H FF30 TCR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU2 16 H FF31 TMDR2 MD3 MD2 MD...

Page 1015: ...1A DTIE0B DTIE0A H FF68 H FF69 H FF6A TCR0 TCR1 TCSR0 CMIEB CMIEB CMFB CMIEA CMIEA CMFA OVIE OVIE OVF CCLR1 CCLR1 ADTE CCLR0 CCLR0 OS3 CKS2 CKS2 OS2 CKS1 CKS1 OS1 CKS0 CKS0 OS0 TMR0 TMR1 16 H FF6B TCSR1 CMFB CMFA OVF OS3 OS2 OS1 OS0 H FF6C TCORA0 H FF6D TCORA1 H FF6E TCORB0 H FF6F TCORB1 H FF70 TCNT0 H FF71 TCNT1 H FF74 write TCSR0 TCNT0 OVF WT IT TME CKS2 CKS1 CKS0 WDT0 16 H FF75 read TCNT0 H FF7...

Page 1016: ...TR AASX AL AAS ADZ ACKB H FF82 SCR1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 H FF83 TDR1 H FF84 SSR1 TDRE RDRF ORER FER PER TEND MPB MPBT SSR1 TDRE RDRF ORER ERS PER TEND MPB MPBT H FF85 RDR1 H FF86 SCMR1 SDIR SINV SMIF ICDR1 SARX1 ICDR7 SVARX6 ICDR6 SVARX5 ICDR5 SVARX4 ICDR4 SVARX3 ICDR3 SVARX2 ICDR2 SVARX1 ICDR1 SVARX0 ICDR0 FSX H FF87 ICMR1 SAR1 MLS SVA6 WAIT SVA5 CKS2 SVA4 CKS1 SVA3 CKS0 SVA2 BC2 SVA...

Page 1017: ...OE1 DAOE0 DAE H FFA8 FLMCR1 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 FLASH 8 H FFA9 FLMCR2 FLER H FFAA EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 H FFAB EBR2 EB11 EB10 EB9 EB8 H FFAC FLPWCR PDWND H FFB0 PORT1 P17 P16 P15 P14 P13 P12 P11 P10 Port 8 H FFB2 PORT3 P37 P36 P35 P34 P33 P32 P31 P30 H FFB3 PORT4 P47 P46 P45 P44 P43 P42 P41 P40 H FFB6 PORT7 P77 P76 P75 P74 P73 P72 P71 P70 H FFB8 PORT9 P97 P96 P95 P94 P9...

Page 1018: ...sables analog output DA1 DA3 1 Enables channel 1 D A conversion Also enables analog output DA1 DA3 D A output enable 0 0 Disables analog output DA0 DA2 1 Enables channel 0 D A conversion Also enables analog output DA0 DA2 D A enable DAOE1 DAOE0 DAE Description 0 0 Disables channel 0 1 channel 2 3 D A conversion 1 0 Enables channel 0 channel 2 D A conversion Disables channel 1 channel 3 D A convers...

Page 1019: ...2 IrCKS1 IrCKS0 0 0 0 B 3 16 3 16ths of bit rate 1 ø 2 1 0 ø 4 1 ø 8 1 0 0 ø 16 1 ø 32 1 0 ø 64 1 ø 128 Bit Initial value R W SCRX Serial Control Register X H FDB4 IIC 7 0 R W 6 IICX1 0 R W 5 IICX0 0 R W 4 IICE 0 R W 3 FLSHE 0 R W 0 0 R W 2 0 R W 1 0 R W I2 C transfer rate select 1 0 I2C master enable 0 Disables CPU access of I2C bus interface data register and control register 1 Enables CPU acces...

Page 1020: ... 1 W 2 1 CLR1 1 W 2 Note 1 Should always be written with 0 2 Always read as 1 Reserved bit Bit Initial value R W IIC clear 3 to 0 CLR3 CLR2 CLR1 CLR0 0 0 1 0 0 1 1 0 1 1 Setting prohibited Setting prohibited IIC0 internal latch cleared IIC1 internal latch cleared IIC0 and IIC1 internal latch cleared Invalid setting ...

Page 1021: ...PWM enable 0 DACNT operates as 14 bit up counter 1 Count stops when DACNT H 0003 Output enable B 0 PWM D A channel B output PWM1 PWM3 output pin disabled 1 PWM D A channel B output PWM1 PWM3 output pin enabled Output enable A 0 PWM D A channel A output PWM0 PWM2 output pin disabled 1 PWM D A channel A output PWM0 PWM2 output pin enabled Output select 0 Direct PWM output 1 Inverted PWM output Clock...

Page 1022: ...4 1 R W 5 3 DA3 1 R W 4 2 DA2 1 R W 3 1 DA1 1 R W 0 1 2 0 DA0 1 R W 1 CFS 1 R W DADRH DADRL DA13 1 R W DA12 1 R W DA11 1 R W DA10 1 R W DA9 1 R W DA6 1 R W DA8 1 R W DA7 1 R W DA5 1 R W DA4 1 R W DA3 1 R W DA2 1 R W DA1 1 R W REGS 1 R W DA0 1 R W CFS 1 R W Carrier frequency select 0 Basic cycle resolution T 64 DADR range H 0401 to H FFFD 1 Basic cycle resolution T 256 DADR range H 0103 to H FFFF C...

Page 1023: ...FDBE H FDBF PWM0 PWM0 PWM1 PWM1 15 7 0 R W 14 6 0 R W 13 5 0 R W 12 4 0 R W 11 3 0 R W 8 0 0 R W 10 2 0 R W 9 1 0 R W 7 8 0 R W 6 9 0 R W 5 10 0 R W 4 11 0 R W 3 12 0 R W 0 REGS 1 R W 2 13 0 R W 1 1 DACNTH DACNTL Register select 0 DADRA and DADRB access enabled 1 DACR and DACNT access enabled Bit CPU Bit counter Initial value R W ...

Page 1024: ...lling edge of ø 8 Internal clock Counting on falling edge of ø 64 Clock input disabled Counter clear 1 0 Clock select 2 to 0 0 1 0 CKS0 0 CKS2 CKS1 0 1 1 External clock Counting on both rising and falling edges External clock Counting on rising edge External clock Counting on falling edge Channel 0 Counting on TCNT1 overflow signal Channel 1 Counting on TCNT0 compare match A Channel 2 Counting on ...

Page 1025: ...TC MRB DISEL bit is 0 Setting When TCNT TCORB 1 Bit 6 Compare match flag A 0 Clearing 1 Reading CMFA then writing 0 to CMFA when CMFA 1 2 When DTC is started by CMIA interrupt and DTC MRB DISEL bit is 0 Setting When TCNT TCORA 1 Bit 5 Timer overflow flag 0 Clearing Reading OVF then writing 0 to OVF when OVF 1 Setting When TCNT changes from H FF to H 00 1 Bit 4 A D trigger enable 0 A D conversion s...

Page 1026: ...Register B1 TCORB2 Time Constant Register B2 TCORB3 Time Constant Register B3 H FF6E H FF6F H FDC6 H FDC7 TMR0 TMR1 TMR2 TMR3 15 1 R W 14 1 R W 13 1 R W 12 1 R W 11 1 R W 10 1 R W 9 1 R W 8 1 R W 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 2 1 R W 1 1 R W 0 1 R W TCORB0 TCORB2 TCORB1 TCORB3 Bit Initial value R W TCNT0 Timer Counter 0 TCNT1 Timer Counter 1 TCNT2 Timer Counter 2 TCNT3 Timer Counter 3 H ...

Page 1027: ... Multiprocessor mode Multiprocessor function disabled Multiprocessor format selected 0 1 Notes 1 When even parity is set parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even In reception a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even 2 When odd parity...

Page 1028: ...ace mode 1 TEND flag set 11 0etu after start of first bit 2 In addition to ON OFF control of clock output High Low control also enabled set by SCR Note etu Elementary Time Unit The time to send one bit Block transfer mode 0 Operation of normal smart card interface mode 1 Error signal output detection and automatic resending of data 2 TXI interrupt generated by TEND flag 3 TEND flag set 12 5etu aft...

Page 1029: ...t Rate Register 1 BRR2 Bit Rate Register 2 BRR3 Bit Rate Register 3 BRR4 Bit Rate Register 4 H FF79 H FF81 H FF89 H FDD1 H FDD9 SCI0 SCI1 SCI2 SCI3 SCI4 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Bit Initial value R W ...

Page 1030: ...al clock SCK pin set for sync clock output 1 0 Async mode External clock SCK pin set for clock input 3 Clock sync mode External clock SCK pin set for sync clock input 1 Async mode External clock SCK pin set for clock input 3 Clock sync mode External clock SCK pin set for sync clock input Notes 1 Clearing the RE bit has no effect on the RDRF FER PER or ORER flags 2 Serial receiving starts on detect...

Page 1031: ...Data Register 1 TDR2 Transmit Data Register 2 TDR3 Transmit Data Register 3 TDR4 Transmit Data Register 4 H FF7B H FF83 H FF8B H FDD3 H FDDB SCI0 SCI1 SCI2 SCI3 SCI4 7 1 R W 6 1 R W 5 1 R W 4 1 R W 3 1 R W 0 1 R W 2 1 R W 1 1 R W Bit Initial value R W ...

Page 1032: ...ious state when the RE bit in SCR is cleared to 0 2 In 2 stop bit mode only the first stop bit is checked for a value of 0 the second stop bit is not checked If a framing error occurs the receive data is transferred to RDR but the RDRF flag is not set Also subsequent serial reception cannot be continued while the FER flag is set to 1 In clocked synchronous mode serial transmission cannot be contin...

Page 1033: ...F8E H FDD6 H FDDE SCI0 SCI1 SCI2 SCI3 SCI4 7 1 6 1 5 1 4 1 3 SDIR 0 R W 0 SMIF 0 R W 2 SINV 0 R W 1 1 Smart card data transfer direction 0 Sends TDR contents LSB first Receive data stored in RDR as LSB first 1 Sends TDR contents MSB first Receive data stored in RDR as MSB first Smart card data invert 0 TDR contents are transmitted without modification Receive data is stored in RDR without modifica...

Page 1034: ...de and watch mode When the SLEEP command is executed in sub active mode operation enters watch mode and high speed mode Output port enable 0 In software standby mode watch mode and during direct transfer the address bus and bus control signal are in the high impedance state 1 In software standby mode watch mode and during direct transfer the address bus and bus control signal remain in the output ...

Page 1035: ...1 Non saturating calculation for MAC instruction Saturating calculation for MAC instruction 0 1 Interrupt control mode 1 0 Interrupt request issued on falling edge of NMI input Interrupt request issued on rising edge of NMI input 0 1 Internal RAM disabled Internal RAM enabled 0 1 NMI edge select RAM Enable Manual reset select bit 0 0 0 Interrupt controlled by bit 1 INTM0 INTM1 Interrupt control mo...

Page 1036: ... ø output High level fixed High impedance 1 High level fixed High level fixed High level fixed High impedance Frequency multiplier switching mode select 0 Specified multiplier valid after transferring to software standby mode watch mode and sub active mode 1 Specified multiplier valid immediately after setting value in STC bit System clock select 2 to 0 SCK2 SCK1 SCK0 0 0 0 1 1 0 1 1 0 0 1 1 Bus m...

Page 1037: ...R W 1 MSTPA1 1 R W 0 MSTPA0 1 R W Module stop 0 DMAC module stop mode is cleared 1 DMAC module stop mode is set Bit Initial value R W MSTPCRB Module Stop Control Register B H FDE9 System 7 MSTPB7 1 R W 6 MSTPB6 1 R W 5 MSTPB5 1 R W 4 MSTPB4 1 R W 3 MSTPB3 1 R W 2 MSTPB2 1 R W 1 MSTPB1 1 R W 0 MSTPB0 1 R W Module stop 0 IIC channel 0 module stop mode canceled 1 Channel 0 module stop mode enabled Mo...

Page 1038: ...ystem 7 MSTPC7 1 R W 6 MSTPC6 1 R W 5 MSTPC5 1 R W 4 MSTPC4 1 R W 3 MSTPC3 1 R W 2 MSTPC2 1 R W 1 MSTPC1 1 R W 0 MSTPC0 1 R W Module stop PC brake controller module stop mode canceled PC brake controller module stop mode enabled 0 1 Bit Initial value R W ...

Page 1039: ...enabled A10 to A23 address output disabled 0 AE2 0 0 0 AE3 0 0 1 1 0 0 A8 to A11 address output enabled A12 to A23 address output disabled A8 to A10 address output enabled A11 to A23 address output disabled A8 to A12 address output enabled A13 to A23 address output disabled 0 1 0 0 1 0 0 1 1 1 A8 to A13 address output enabled A14 to A23 address output disabled A8 to A14 address output enabled A15 ...

Page 1040: ...h mode When the SLEEP command is executed in sub active mode operation transfers to watch mode or directly to high speed mode Operation transfers to high speed mode after watch mode is canceled 1 When the SLEEP command is executed in high speed mode operation transfers to watch mode or sub active mode When the SLEEP command is executed in sub active mode operation transfers to sub sleep mode or wa...

Page 1041: ... R W BAA 22 22 0 R W BAA 21 21 0 R W BAA 20 20 0 R W BAA 19 19 0 R W BAA 18 18 0 R W BAA 17 17 0 R W BAA 16 16 0 R W 0 BAA 7 7 R W 0 BAA 6 6 R W 0 BAA 5 5 R W 0 BAA 4 4 R W 0 BAA 3 3 R W 0 BAA 2 2 R W 0 BAA 1 1 R W 0 BAA 0 0 Break address 23 to 0 Note The bit configuration of BARB is the same as that of BARA Bit Initial value R W ...

Page 1042: ...bits masked and not included in break condition BAA11 to BAA0 low 12 bits masked and not included in break condition BAA15 to BAA0 low 16 bits masked and not included in break condition 0 BAMRA 1 0 0 BAMRA 2 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1 1 When the CPU is the bus master PC break performed When the CPU or DTC is the bus master PC break performed 0 1 Clearing Writing 0 to CMFA after reading CM...

Page 1043: ...ue R W ISCRH IRQ7 sense control A B to IRQ0 sense control A 0 0 Interrupt request issued when IRQ7 to IRQ0 input level low Interrupt request issued on falling edge of IRQ7 to IRQ0 input Interrupt request issued on rising edge of IRQ7 to IRQ0 input Interrupt request issued on both falling and rising edge of IRQ7 to IRQ0 input IRQ7SCA to IRQ0SCA IRQ7SCB to IRQ0SCB 1 0 1 1 IER IRQ Enable Register H F...

Page 1044: ... When IRQn interrupt exception processing is executed when set for rising edge or falling edge or both rising edge and falling edge detection IRQnSCB 1 and IRQnSCA 1 4 When the DTC starts due to IRQn interrupt and the DTC MRB DISEL bit is 0 Setting 1 When the IRQn input level changes to LOW when set for LOW level detection IRQnSCB IRQnSCA 0 2 When a falling edge occurs at the IRQn input when set f...

Page 1045: ...2 0 R W 1 DTCE1 0 R W DTC startup by interrupt disabled Clearing When data transmission ends with the DISEL bit 1 On completion of the specified number of transmissions 0 1 DTC start enable 0 DTC startup by interrupt enabled Retention When DISEL 0 and the specified number of transmissions has not completed DTCEn n 7 to 0 Bit Initial value R W ...

Page 1046: ...oftware startup enable DTC software startup disabled Clearing When DISEL 0 and the specified number of transmissions has not completed When 0 is written after a software startup data transmit end interrupt SWDTEND request is sent to the CPU 0 1 DTC software startup vector 6 to 0 0 DTC software startup enabled Retention When DISEL 1 and data transmission ends On completion of the specified number o...

Page 1047: ...annel 2 compare match 1 TPU channel 3 compare match Pulse output group 3 output trigger 0 0 TPU channel 0 compare match G1CMS0 G1CMS1 1 TPU channel 1 compare match 0 1 TPU channel 2 compare match 1 TPU channel 3 compare match Pulse output group 1 output trigger 0 0 TPU channel 0 compare match G0CMS0 G0CMS1 1 TPU channel 1 compare match 0 1 TPU channel 2 compare match 1 TPU channel 3 compare match ...

Page 1048: ...RH 1 0 1 0 Pulse output group 3 set for direct output pin output level is set HIGH when PODRH 1 Pulse output group 3 set for normal operation output value updated on compare match A for selected TPU 0 1 0 Pulse output group 3 set for non overlap operation 1 output and 0 output can be output independently on compare matches A and B of selected TPU Pulse output group 2 set for normal operation outpu...

Page 1049: ...DER0 0 R W 2 NDER2 0 R W 1 NDER1 0 R W NDERL Next data enable 15 to 8 0 1 NDER15 to NDER8 Pulse output PO15 to PO8 disabled transfer from NDR15 NDR8 to POD15 POD8 disabled Pulse output PO15 to PO8 enabled transfer from NDR15 NDR8 to POD15 POD8 enabled Next data enable 7 to 0 0 1 NDER7 to NDER0 Pulse output PO7 to PO0 disabled transfer from NDR7 NDR0 to POD7 POD0 disabled Pulse output PO7 to PO0 en...

Page 1050: ...0 R W 5 POD13 0 R W 4 POD12 0 R W 3 POD11 0 R W 0 POD8 0 R W 2 POD10 0 R W 1 POD9 0 R W PODRH 7 POD7 0 R W 6 POD6 0 R W 5 POD5 0 R W 4 POD4 0 R W 3 POD3 0 R W 0 POD0 0 R W 2 POD2 0 R W 1 POD1 0 R W Note The bits set for pulse output by NDER are read only bits PODRL Bit Initial value R W Bit Initial value R W ...

Page 1051: ...R W Same trigger for pulse output groups 7 1 6 1 5 1 4 1 3 1 0 1 2 1 1 1 Bit Initial value R W 7 NDR15 0 R W 6 NDR14 0 R W 5 NDR13 0 R W 4 NDR12 0 R W 3 1 0 1 2 1 1 1 Bit Initial value R W Different triggers for pulse output groups 7 1 6 1 5 1 4 1 3 NDR11 0 R W 0 NDR8 0 R W 2 NDR10 0 R W 1 NDR9 0 R W Bit Initial value R W Note For details see section 12 2 4 Notes on NDR Access ...

Page 1052: ... NDR0 0 R W 2 NDR2 0 R W 1 NDR1 0 R W Bit Initial value R W 7 NDR7 0 R W 6 NDR6 0 R W 5 NDR5 0 R W 4 NDR4 0 R W 3 1 0 1 2 1 1 1 Bit Initial value R W Different triggers for pulse output groups Note For details see section 12 2 4 Notes on NDR Access Same trigger for pulse output groups P1DDR Port 1 Data Direction Register H FE30 Port 7 P17DDR 0 W 6 P16DDR 0 W 5 P15DDR 0 W 4 P14DDR 0 W 3 P13DDR 0 W ...

Page 1053: ...Initial value R W PADDR Port A Data Direction Register H FE39 Port 7 Undefined 6 Undefined 5 Undefined 4 Undefined 3 PA3DDR 0 W 0 PA0DDR 0 W 2 PA2DDR 0 W 1 PA1DDR 0 W Bit Initial value R W PBDDR Port B Data Direction Register H FE3A Port 7 PB7DDR 0 W 6 PB6DDR 0 W 5 PB5DDR 0 W 4 PB4DDR 0 W 3 PB3DDR 0 W 0 PB0DDR 0 W 2 PB2DDR 0 W 1 PB1DDR 0 W Bit Initial value R W PCDDR Port C Data Direction Register...

Page 1054: ...Direction Register H FE3D Port 7 PE7DDR 0 W 6 PE6DDR 0 W 5 PE5DDR 0 W 4 PE4DDR 0 W 3 PE3DDR 0 W 0 PE0DDR 0 W 2 PE2DDR 0 W 1 PE1DDR 0 W Bit Initial value R W PFDDR Port F Data Direction Register H FE3E Port 7 PF7DDR 1 W 0 W 6 PF6DDR 0 W 0 W 5 PF5DDR 0 W 0 W 4 PF4DDR 0 W 0 W 3 PF3DDR 0 W 0 W 0 PF0DDR 0 W 0 W 2 PF2DDR 0 W 0 W 1 PF1DDR 0 W 0 W Bit Mode 4 to 6 Initial value R W Mode 7 Initial value R W...

Page 1055: ...rt 7 Undefined 6 Undefined 5 Undefined 4 Undefined 3 PA3PCR 0 R W 0 PA0PCR 0 R W 2 PA2PCR 0 R W 1 PA1PCR 0 R W Bit Initial value R W PBPCR Port B Pull Up MOS Control Register H FE41 Port 7 PB7PCR 0 R W 6 PB6PCR 0 R W 5 PB5PCR 0 R W 4 PB4PCR 0 R W 3 PB3PCR 0 R W 0 PB0PCR 0 R W 2 PB2PCR 0 R W 1 PB1PCR 0 R W Bit Initial value R W PCPCR Port C Pull Up MOS Control Register H FE42 Port 7 PC7PCR 0 R W 6 ...

Page 1056: ... PE5PCR 0 R W 4 PE4PCR 0 R W 3 PE3PCR 0 R W 0 PE0PCR 0 R W 2 PE2PCR 0 R W 1 PE1PCR 0 R W Bit Initial value R W P3ODR Port 3 Open Drain Control Register H FE46 Port 7 P37ODR 0 R W 6 P36ODR 0 R W 5 P35ODR 0 R W 4 P34ODR 0 R W 3 P33ODR 0 R W 0 P30ODR 0 R W 2 P32ODR 0 R W 1 P31ODR 0 R W Bit Initial value R W PAODR Port A Open Drain Control Register H FE47 Port 7 Undefined 6 Undefined 5 Undefined 4 Und...

Page 1057: ... 0 R W 4 PB4ODR 0 R W 3 PB3ODR 0 R W 0 PB0ODR 0 R W 2 PB2ODR 0 R W 1 PB1ODR 0 R W Bit Initial value R W PCODR Port C Open Drain Control Register H FE49 Port 7 PC7ODR 0 R W 6 PC6ODR 0 R W 5 PC5ODR 0 R W 4 PC4ODR 0 R W 3 PC3ODR 0 R W 0 PC0ODR 0 R W 2 PC2ODR 0 R W 1 PC1ODR 0 R W Bit Initial value R W ...

Page 1058: ...l clock counts on ø 16 0 1 0 0 1 External clock counts on TCLKA pin input 0 1 Internal clock counts on ø 1024 1 Internal clock counts on ø 64 1 Internal clock counts on ø 256 0 1 Internal clock counts on ø 4096 0 0 Internal clock counts on ø 1 Internal clock counts on ø 4 1 Internal clock counts on ø 16 0 1 0 0 1 External clock counts on TCLKA pin input 0 1 External clock counts on TCLKB pin input...

Page 1059: ...RA operation Buffer operation of TGRA and TGRC Normal operation Reserved PWM mode 1 PWM mode 2 Phase calculation mode 1 Phase calculation mode 2 Phase calculation mode 3 Phase calculation mode 4 0 1 Buffer operation B Mode 3 to 0 Buffer operation A 0 1 0 MD0 MD1 MD2 2 0 0 1 1 0 0 1 1 0 1 1 MD3 1 0 1 Don t care Notes 1 2 MD3 is a reserved bit Only write 0 to this bit Phase calculation mode cannot b...

Page 1060: ...ut source is TIOCA3 pin Capture input source is channel 4 count clock 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don t care TGR3B I O Control 0 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Inpu...

Page 1061: ...abled Initial output is 1 output Capture input source is TIOCA4 pin Capture input source is TGR3A compare match input capture 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don t care TGR4B I O Control 0 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input ...

Page 1062: ...register Output disabled Initial output is 0 output Output disabled Initial output is 1 output Capture input source is TIOCA5 pin 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don t care TGR5B I O Control 0 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input ...

Page 1063: ...n Capture input source is channel 1 count clock 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don t care TGR0B I O Control 0 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT1 cou...

Page 1064: ...t disabled Initial output is 1 output Capture input source is TIOCA1 pin Capture input source is TGR0A compare match input capture 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don t care TGR1B I O Control 0 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge I...

Page 1065: ...register Output disabled Initial output is 0 output Output disabled Initial output is 1 output Capture input source is TIOCA2 pin 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Don t care TGR2B I O Control 0 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input ...

Page 1066: ...re match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT4 count up count down 1 TGR3D is output compare register 2 TGR3D is input capture register 2 Output disabled Initial output is 0 output Output disabled Initial output is 1 output Capture input source is TIOCD3 pin Capture inpu...

Page 1067: ...re match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT1 count up count down 1 TGR0D is output compare register 2 TGR0D is input capture register 2 Output disabled Initial output is 0 output Output disabled Initial output is 1 output Capture input source is TIOCD0 pin Capture inpu...

Page 1068: ...rupt enable A Overflow interrupt enable TGFB bit interrupt request TGIB disabled TGFB bit interrupt request TGIB enabled 0 1 TGFD bit interrupt request TGID disabled TGFD bit interrupt request TGID enabled 0 1 A D conversion start request generation disabled A D conversion start request generation enabled 0 1 TCFV interrupt request TCIV disabled TCFV interrupt request TCIV enabled 0 1 TGR interrup...

Page 1069: ...ting 1 When TGRC is functioning as the output compare register and TCNT TGRC 2 When TGRC is functioning as the input capture register and the value of TCNT is sent to TGRC by the input capture signal 0 1 Clearing 1 When the DTC is started by a TGIB interrupt and the DTC MRB DISEL bit is 0 2 Writing 0 to TGFB after reading TGFB 1 Setting 1 When TGRB is functioning as the output compare register and...

Page 1070: ...3 TPU4 TPU5 15 0 R W 14 0 R W 13 0 R W 12 0 R W 11 0 R W 8 0 R W 10 0 R W 9 0 R W 7 0 R W 6 0 R W 5 0 R W 4 0 R W 3 0 R W 0 0 R W 2 0 R W 1 0 R W Note This register can be used as an up down counter only in phase calculation mode and when counting overflows and underflows in other channels in phase calculation mode In all other cases this register functions as an up counter Bit Initial value R W ...

Page 1071: ...Timer General Register 3C TGR3D Timer General Register 3D TGR4A Timer General Register 4A TGR4B Timer General Register 4B TGR5A Timer General Register 5A TGR5B Timer General Register 5B H FF18 H FF1A H FF1C H FF1E H FF28 H FF2A H FF38 H FF3A H FE88 H FE8A H FE8C H FE8E H FE98 H FE9A H FEA8 H FEAA TPU0 TPU0 TPU0 TPU0 TPU1 TPU1 TPU2 TPU2 TPU3 TPU3 TPU3 TPU3 TPU4 TPU4 TPU5 TPU5 15 1 R W 14 1 R W 13 1...

Page 1072: ...ternal clock counts on ø 16 0 1 0 0 1 External clock counts on TCLKA pin input 0 1 External clock counts on TCLKB pin input 1 Internal clock counts on ø 64 1 External clock counts on TCLKC pin input 0 1 Internal clock counts on ø 1024 0 0 Internal clock counts on ø 1 Internal clock counts on ø 4 1 Internal clock counts on ø 16 0 1 0 0 1 External clock counts on TCLKA pin input 0 1 External clock c...

Page 1073: ...l 1 TMDR1 Channel 2 TMDR2 Channel 4 TMDR4 Channel 5 TMDR5 Normal operation Reserved PWM mode 1 PWM mode 2 Phase calculation mode 1 Phase calculation mode 2 Phase calculation mode 3 Phase calculation mode 4 Mode 3 to 0 0 1 0 MD0 MD1 MD2 2 0 0 1 1 0 0 1 1 0 1 1 MD3 1 0 1 Don t care Note 1 2 MD3 is a reserved bit Only write 0 to this bit Phase calculation mode cannot be set for channels 0 and 3 Only ...

Page 1074: ...el 5 TIER5 A D conversion start request enable TGFA bit interrupt request TGIA disabled TGFA bit interrupt request TGIA enabled 0 1 TGR interrupt enable A Underflow interrupt enable TGFB bit interrupt request TGIB disabled TGFB bit interrupt request TGIB enabled 0 1 0 1 A D conversion start request generation disabled A D conversion start request generation enabled 0 1 TCFU interrupt request TCIU ...

Page 1075: ...TGRB is functioning as the input capture register and the value of TCNT is sent to TGRB by the input capture signal 0 1 Clearing 1 When the DTC is started by a TGIA interrupt and the DTC MRB DISEL bit is 0 2 When the DMAC is started by a TGIA interrupt and the DMAC DMABCR DTA bit is 1 3 Writing 0 to TGFA after reading TGFA 1 Setting 1 When TGRA is functioning as the output compare register and TCN...

Page 1076: ...itial output value by writing to TIOR n 5 to 0 Bit Initial value R W TSYR Timer Synchro Register H FEB1 TPU Common 7 0 6 0 5 SYNC5 0 R W 4 SYNC4 0 R W 3 SYNC3 0 R W 0 SYNC0 0 R W 2 SYNC2 0 R W 1 SYNC1 0 R W Bit Initial value R W Timer sync 5 to 0 TCNTn operate independently TCNTs are preset and cleared independently of other channels TCNTn operate in sync mode Synchronized TCNT presetting and clea...

Page 1077: ... H FEC1 H FEC2 H FEC3 H FEC4 H FEC5 H FEC6 H FEC7 H FEC8 H FEC9 H FECA H FECB H FECE Interrupt Controller 7 0 6 IPR6 1 R W 5 IPR5 1 R W 4 IPR4 1 R W 3 0 0 IPR0 1 R W 2 IPR2 1 R W 1 IPR1 1 R W IPRB IRQ2 Register Bit IRQ3 IPRC IRQ6 IRQ7 IRQ4 IRQ5 DTC Interrupt factors vs IPR IPRA IRQ0 IRQ1 IPRD Watchdog timer 0 Refresh timer IPRE PC brake ADC Watchdog timer 1 IPRF TPU channel 0 TPU channel 1 IPRG TP...

Page 1078: ...it Mode 5 to 7 Initial value R W Mode 4 Initial value R W ASTCR Access State Control Register H FED1 Bus Controller 7 AST7 1 R W 6 AST6 1 R W 5 AST5 1 R W 4 AST4 1 R W 3 AST3 1 R W 0 AST0 1 R W 2 AST2 1 R W 1 AST1 1 R W Area 7 to 0 access state control Area n set as 2 state access area Insertion of wait states in area n external area access is disabled External area access of area n set as 3 state...

Page 1079: ...ait state inserted when accessing external area of area 5 2 program wait states inserted when accessing external area of area 5 3 program wait states inserted when accessing external area of area 5 W50 W51 1 0 1 1 0 0 No program wait inserted when accessing external area of area 4 1 program wait state inserted when accessing external area of area 4 2 program wait states inserted when accessing ext...

Page 1080: ... inserted when accessing external area of area 1 2 program wait states inserted when accessing external area of area 1 3 program wait states inserted when accessing external area of area 1 W10 W11 1 0 1 1 0 0 No program wait inserted when accessing external area of area 0 1 program wait state inserted when accessing external area of area 0 2 program wait states inserted when accessing external are...

Page 1081: ...1 Idle cycle insertion 0 Area 0 is basic bus interface Initial value Area 0 is burst ROM interface 0 1 Burst ROM enable Burst cycle 1 state Burst cycle 2 states 0 1 Burst access 4 words max Burst access 8 words max 0 1 Burst cycle select 1 RAM type select Burst cycle select 0 Note When all areas selected in the DRAM area are set for 8 bit access the PF2 pin can be used as an I O port or BREQO or W...

Page 1082: ... as port or as CS3 signal output When only area 2 is set as DRAM or when areas 2 to 5 are set as contiguous DRAM space the CS3 pin is used as the OE pin 0 1 OE select Do not use write data buffer function Use write data buffer function 0 1 Write data buffer enable CAS signal output timing is the same when reading and writing When reading the CAS signal is asserted one half cycle faster than when w...

Page 1083: ...state Insert 2 wait states Do not insert wait state Reserved bit Refresh cycle wait control 1 0 Multiplex shift count 1 0 0 1 0 RLW0 RLW1 0 1 1 9 bit shift 1 When set for 8 bit access space Row addresses A23 to A9 are targets of comparison 2 When set for 16 bit access space Row addresses A23 to A10 are targets of comparison 10 bit shift 1 When set for 8 bit access space Row addresses A23 to A10 ar...

Page 1084: ...andby mode 0 1 External access enabled at CAS before RAS refresh External access disabled at CAS before RAS refresh 0 1 Do not perform refresh control Perform refresh control 0 1 Refresh mode CMF flag interrupt request CMI disabled CMF flag interrupt request CMI enabled Counting on ø 8 Counting on ø 32 No counting operation Counting on ø 2 0 1 Compare match flag Refresh counter clock select Compar...

Page 1085: ... t care Emulation not selected Program erase protection of all flash memory blocks is disabled 0 1 Flash memory area selection 0 Emulation selected Program erase protection of all flash memory blocks is enabled Addresses Block Name RAMS RAM1 RAM1 RAM0 H FFD000 H FFDFFF RAM area 4 kbytes 0 H 000000 H 000FFF EB0 4 kbytes 1 0 0 0 H 001000 H 001FFF EB1 4 kbytes 1 0 0 1 H 002000 H 002FFF EB2 4 kbytes 1...

Page 1086: ...ndefined Bit MAR Initial value R W Bit MAR Initial value R W In short address mode Specifies transfer destination transfer source address In full address mode Not used IOAR0A I O Address Register 0A IOAR1A I O Address Register 1A H FEE4 H FEF4 DMAC DMAC 0 R W 2 R W 1 R W 3 R W 4 R W 5 R W 6 R W 7 R W 8 R W 9 R W 10 R W 11 R W 12 R W 13 R W 14 R W 15 R W Undefined Bit IOAR Initial value R W In shor...

Page 1087: ... number of transfers Holds block size MAR0BH Memory Address Register 0BH MAR0BL Memory Address Register 0BL H FEE8 H FEEA DMAC DMAC Undefined Bit MAR0BL Initial value R W 15 R W 14 R W 13 R W 12 R W 11 R W 10 R W 9 R W 8 R W 7 R W 6 R W 5 R W 4 R W 3 R W 2 R W 1 R W 0 R W Bit MAR0BH Initial value R W 31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 R W 22 R W 21 R W 20 R W 19 R W 18 R W 17 R W 16 R W In...

Page 1088: ...mode Specifies transfer destination transfer source address In full address mode Not used ETCR0B Transfer Count Register 0B H FEEE DMAC Undefined Note Not used in normal mode Bit ETCR0B Initial value R W Sequential mode and idle mode Repeat mode Block transfer mode 15 R W 14 R W 13 R W 12 R W 11 R W 10 R W 9 R W 8 R W 7 R W 6 R W 5 R W 4 R W 3 R W 2 R W 1 R W 0 R W Transfer counter Transfer counte...

Page 1089: ... R W 22 R W 21 R W 20 R W 19 R W 18 R W 17 R W 16 R W In short address mode Specifies transfer destination transfer source address In full address mode Not used ETCR1A Transfer Count Register 1A H FEF6 DMAC Undefined Bit ETCR1A Initial value R W Sequential mode Idle mode Normal mode Repeat mode Block transfer mode 15 R W 14 R W 13 R W 12 R W 11 R W 10 R W 9 R W 8 R W 7 R W 6 R W 5 R W 4 R W 3 R W ...

Page 1090: ... 22 R W 21 R W 20 R W 19 R W 18 R W 17 R W 16 R W In short address mode Specifies transfer destination transfer source address In full address mode Not used ETCR1B Transfer Count Register 1B H FEFE DMAC Undefined Note Not used in normal mode Bit ETCR1B Initial value R W Sequential mode and idle mode Repeat mode Block transfer mode 15 R W 14 R W 13 R W 12 R W 11 R W 10 R W 9 R W 8 R W 7 R W 6 R W 5...

Page 1091: ...Bit Initial value R W P7DR Port 7 Data Register H FF06 Port 7 P77DR 0 R W 6 P76DR 0 R W 5 P75DR 0 R W 4 P74DR 0 R W 3 P73DR 0 R W 0 P70DR 0 R W 2 P72DR 0 R W 1 P71DR 0 R W Bit Initial value R W PADR Port A Data Register H FF09 Port 7 Undefined 6 Undefined 5 Undefined 4 Undefined 3 PA3DR 0 R W 0 PA0DR 0 R W 2 PA2DR 0 R W 1 PA1DR 0 R W Bit Initial value R W PBDR Port B Data Register H FF0A Port 7 PB...

Page 1092: ...it Initial value R W PEDR Port E Data Register H FF0D Port 7 PE7DR 0 R W 6 PE6DR 0 R W 5 PE5DR 0 R W 4 PE4DR 0 R W 3 PE3DR 0 R W 0 PE0DR 0 R W 2 PE2DR 0 R W 1 PE1DR 0 R W Bit Initial value R W PFDR Port F Data Register H FF0E Port 7 PF7DR 0 R W 6 PF6DR 0 R W 5 PF5DR 0 R W 4 PF4DR 0 R W 3 PF3DR 0 R W 0 PF0DR 0 R W 2 PF2DR 0 R W 1 PF1DR 0 R W Bit Initial value R W PGDR Port G Data Register H FF0F Po...

Page 1093: ...ing to all DMACR0A bits and DMABCR bits 8 4 and 0 Initial value Enables writing to all DMACR0A bits and DMABCR bits 8 4 and 0 0 1 Write enable 0B Disables writing to all DMACR0B bits DMABCR bits 9 5 and 1 and DMATCR bit 4 Initial value Enables writing to all DMACR0B bits DMABCR bits 9 5 and 1 and DMATCR bit 4 0 1 Write enable 0A Write enable 1B Bit DMAWER Initial value R W DMATCR DMA Terminal Cont...

Page 1094: ... 1 0 1 0 1 Transfer in block transfer mode destination is block area Transfer in normal mode Transfer in block transfer mode source is block area Source Address Increment Decrement 0 MARA is fixed 1 0 1 0 1 MARA is incremented after a data transfer MARA is fixed MARA is decremented after a data transfer Data Transfer Size 0 Byte size transfer 1 Word size transfer When DTSZ 0 MARA is incremented by...

Page 1095: ...burst 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 0 1 0 0 1 1 1 1 Activated by TPU channel 0 compare match input capture A interrupt Activated by TPU channel 1 compare match input capture A interrupt Activated by TPU channel 2 compare match input capture A interrupt Activated by TPU channel 3 compare match input capture A interrupt Activated by TPU channel 4 compare match input capture A interrupt Activated by ...

Page 1096: ... by TPU channel 4 compare match input capture A interrupt Activated by TPU channel 5 compare match input capture A interrupt 0 1 0 1 0 0 1 1 0 1 Data Transfer Direction 0 0 1 Transfer with MAR as source address and IOAR as destination address Transfer with IOAR as source address and MAR as destination address 1 0 1 Transfer with MAR as source address and DACK pin as write strobe Transfer with DACK...

Page 1097: ...led 0 1 Clearing of selected internal interrupt factor at DMA transfer disabled Clearing of selected internal interrupt factor at DMA transfer enabled 0 1 Full address enable 0 Transfer in dual address mode Transfer in single address mode 0 1 Single address enable 1 Single address enable 0 Data transfer acknowledge 0B Data transfer acknowledge 1A Data transfer acknowledge 1B Data transfer enable 1...

Page 1098: ...Short address mode 1 Full address mode Data transfer acknowledge 1 Data transfer acknowledge 0 0 Clearing of selected internal interrupt source at time of DMA transfer is disabled 1 Clearing of selected internal interrupt source at time of DMA transfer is enabled 0 Clearing of selected internal interrupt source at time of DMA transfer is disabled 1 Clearing of selected internal interrupt source at...

Page 1099: ... enable 0B 0 Transfer break interrupt disabled 1 Transfer break interrupt enabled Data transfer interrupt enable 1B 0 Transfer break interrupt disabled 1 Transfer break interrupt enabled Data transfer enable 0 0 Data transfer disabled 1 Data transfer enabled Data transfer enable 1 0 Data transfer disabled 1 Data transfer enabled Data transfer master enable 0 0 Data transfer disabled In normal mode...

Page 1100: ...ernal reset Timer enable 0 Initializes TCNT to H 00 and disables the counting operation 1 TCNT performs counting operation Timer mode select 0 Interval timer mode Interval timer interrupt WOVI request sent to CPU when overflow occurs at TCNT 1 Watchdog timer mode WDTOVF signal output externally when overflow occurs at TCNT Note See Section 15 2 3 Reset control status register RSTCSR for details of...

Page 1101: ...STS 0 R W 4 1 3 1 0 1 2 1 1 1 Notes Only 0 can be written to these bits to clear these flags TCNT is write protected by a password to prevent accidental overwriting For details see section 15 2 5 Notes on Register Access Watchdog timer overflow flag 0 Clearing Writing 0 to WOVF after reading TCSR when WOVF 1 1 Setting When in watchdog timer mode TCNT overflows H FF H 00 Reset select 0 Power on res...

Page 1102: ...ternal states initialized SAR and SARX can be accessed 1 I2C bus interface module enabled for transfer operations pins SCL and SCA are driving the bus ICMR and ICDR can be accessed Acknowledge bit judgement selection 0 The value of the acknowledge bit is ignored and continuous transfer is performed 1 If the acknowledge bit is 1 continuous transfer is interrupted Start condition stop condition proh...

Page 1103: ...2 When start conditions are detected 3 In master mode 1 2nd slave address confirmed Setting When 2nd slave address is detected in slave receive mode and FSX 0 Arbitration lost flag 0 Secure bus Clearing 1 When data is written to ICDR when sending or when data is read when receiving 2 When 0 is written after reading AL 1 1 Bus arbitration lost Setting 1 When there is a mismatch between internal SDA...

Page 1104: ...CDRS6 5 ICDRS5 4 ICDRS4 3 ICDRS3 0 ICDRS0 2 ICDRS2 1 ICDRS1 7 ICDRT7 W 6 ICDRT6 W 5 ICDRT5 W 4 ICDRT4 W 3 ICDRT3 W 0 ICDRT0 W 2 ICDRT2 W 1 ICDRT1 W RDRF 0 TDRE 0 Bit Initial value R W Bit Initial value R W Bit Initial value R W Bit Initial value R W Bit Initial value R W SARX0 2nd Slave Address Register SARX1 2nd Slave Address Register H FF7E H FF86 IIC0 IIC1 7 SVAX6 0 R W 6 SVAX5 0 R W 5 SVAX4 0 ...

Page 1105: ...13 kHz 391 kHz 1 0 0 ø 80 62 5kHz 100 kHz 125 kHz 200 kHz 250 kHz 313 kHz 1 ø 100 50 0kHz 80 0 kHz 100 kHz 160 kHz 200 kHz 250 kHz 1 0 ø 112 44 6kHz 71 4 kHz 89 3 kHz 143 kHz 179 kHz 223 kHz 1 ø 128 39 1kHz 62 5 kHz 78 1 kHz 125 kHz 156 kHz 195 kHz 1 0 0 0 ø 56 89 3kHz 143 kHz 179 kHz 286 kHz 357 kHz 446 kHz 1 ø 80 62 5kHz 100 kHz 125 kHz 200 kHz 250 kHz 313 kHz 1 0 ø 96 52 1kHz 83 3 kHz 104 kHz 1...

Page 1106: ...rmat SAR slave address ignored SARX slave address recognized 1 Synchronous serial format SAR and SARX slave addresses ignored 1 Must not be set Bit Initial value R W ADDRAH A D Data Register AH ADDRAL A D Data Register AL ADDRBH A D Data Register BH ADDRBL A D Data Register BL ADDRCH A D Data Register CH ADDRCL A D Data Register CL ADDRDH A D Data Register DH ADDRDL A D Data Register DL H FF90 H F...

Page 1107: ...s to be sequentially converted until this bit is cleared to 0 by a software reset or standby mode is selected or module stop mode is selected A D interrupt enable 0 A D conversion end interrupt ADI requests disabled 1 A D conversion end interrupt ADI requests enabled Scan mode 0 Single mode 1 Scan mode Channel select 3 0 AN8 to AN11 set as group 0 analog input pins and AN12 to AN15 as group 1 anal...

Page 1108: ...rsion by software 1 Enables starting of A D conversion by TPU conversion start trigger 1 0 Enables starting of A D conversion by 8 bit timer conversion start trigger 1 Enables starting of A D conversion by external trigger pin ADTRG CKS1 CKS0 Description 0 0 Conversion time 530 states Max 1 Conversion time 266 states Max 1 0 Conversion time 134 states Max 1 Conversion time 68 states Max Bit Initia...

Page 1109: ...g operation Prescaler select 0 TCNT counts the divided clock output by the ø based prescaler 1 TCNT counts the divided clock output by the øSUB based prescaler PSS Reset or NMI 0 NMI interrupt request 1 Internal reset request Timer mode select 0 Interval timer mode Interval timer interrupt WOVI request sent to CPU when overflow occurs at TCNT 1 Watchdog timer mode Reset or NMI interrupt request se...

Page 1110: ...d Setting When FWE 1 Erase setup bit 1 0 Exits erase setup 1 Erase setup Setting When FWE 1 and SWE1 1 Program setup bit 1 0 Exits program setup 1 Program setup Setting When FWE 1 and SWE1 1 Erase verify 1 0 Exits erase verify mode 1 Enters erase verify mode Setting When FWE 1 and SWE1 1 Program verify 1 0 Exits program verify mode 1 Enters program verify mode Setting When FWE 1 and SWE1 1 Erase 1...

Page 1111: ...n error has occurred when writing to or erasing flash memory Flash memory protection against writing and erasing error protection is enabled Setting See 22 8 3 Error Protection Bit Initial value R W EBR1 Erase Block Register 1 H FFAA FLASH 7 EB7 0 R W 6 EB6 0 R W 5 EB5 0 R W 4 EB4 0 R W 3 EB3 0 R W 0 EB0 0 R W 2 EB2 0 R W 1 EB1 0 R W Bit Initial value R W EBR2 Erase Block Register 2 H FFAB FLASH 7...

Page 1112: ...ition to flash memory power down mode disabled Bit Initial value R W PORT1 Port 1 Register H FFB0 Port 7 P17 R 6 P16 R 5 P15 R 4 P14 R 3 P13 R 0 P10 R 2 P12 R 1 P11 R Bit Initial value R W Note Determined by status of pins P17 to P10 PORT3 Port 3 Register H FFB2 Port 7 P37 R 6 P36 R 5 P35 R 4 P34 R 3 P33 R 0 P30 R 2 P32 R 1 P31 R Bit Initial value R W Note Determined by status of pins P37 to P30 ...

Page 1113: ...it Initial value R W PORT7 Port 7 Register H FFB6 Port 7 P77 R 6 P76 R 5 P75 R 4 P74 R 3 P73 R 0 P70 R 2 P72 R 1 P71 R Note Determined by status of pins P77 to P70 Bit Initial value R W PORT9 Port 9 Register H FFB8 Port 7 P97 R 6 P96 R 5 P95 R 4 P94 R 3 P93 R 0 P90 R 2 P92 R 1 P91 R Note Determined by status of pins P97 to P90 Bit Initial value R W ...

Page 1114: ...B5 R 4 PB4 R 3 PB3 R 0 PB0 R 2 PB2 R 1 PB1 R Note Determined by status of pins PB7 to PB0 Bit Initial value R W PORTC Port C Register H FFBB Port 7 PC7 R 6 PC6 R 5 PC5 R 4 PC4 R 3 PC3 R 0 PC0 R 2 PC2 R 1 PC1 R Note Determined by status of pins PC7 to PC0 Bit Initial value R W PORTD Port D Register H FFBC Port 7 PD7 R 6 PD6 R 5 PD5 R 4 PD4 R 3 PD3 R 0 PD0 R 2 PD2 R 1 PD1 R Note Determined by status...

Page 1115: ...tial value R W PORTF Port F Register H FFBE Port 7 PF7 R 6 PF6 R 5 PF5 R 4 PF4 R 3 PF3 R 0 PF0 R 2 PF2 R 1 PF1 R Note Determined by status of pins PF7 to PF0 Bit Initial value R W PORTG Port G Register H FFBF Port 7 Undefined 6 Undefined 5 Undefined 4 PG4 R 3 PG3 R 0 PG0 R 2 PG2 R 1 PG1 R Note Determined by status of pins PG4 to PG0 Bit Initial value R W ...

Page 1116: ...utput enable DMA transfer acknowledge enable Pulse output DMA transfer acknowledge Output compare Output PWM output enable Output compare output PWM output Input capture input WDDR1 WDR1 RDR1 RPOR1 n 0 1 Note Write to P1DDR Write to P1DR Read P1DR Read port 1 Legend Priority order Address output Output compare output PWM output DMA transfer acknowledge output pulse output DR output Internal addres...

Page 1117: ...pare output PWM output enable Output compare output PWM output Pulse output External clock input Input capture input Legend WDDR1 Write to P1DDR WDR1 Write to P1DR RDR1 Read P1DR RPOR1 Read port 1 n 2 or 3 Note Priority order address output output compare output PWM output pulse output DR output Internal data bus Internal address bus Figure C 1 b Port 1 Block Diagram Pins P12 and P13 ...

Page 1118: ...0 interrupt input Output compare output PWM output enable Output compare output PWM output Pulse output Input capture input Legend WDDR1 Write to P1DDR WDR1 Write to P1DR RDR1 Read P1DR RPOR1 Read port 1 Note Priority order output compare output PWM output pulse output DR output Internal data bus Figure C 1 c Port 1 Block Diagram Pin P14 ...

Page 1119: ...e output PWM output enable Output compare output PWM output Pulse output Input capture input External clock input Legend WDDR1 Write to P1DDR WDR1 Write to P1DR RDR1 Read P1DR RPOR1 Read port 1 Note Priority order output compare output PWM output pulse output DR output Internal data bus Figure C 1 d Port 1 Block Diagram Pin P15 ...

Page 1120: ...t enable Output compare output PWM output Pulse output PWM module PWM2 output enable PWM2 output Input capture input Input controller IRQ1 interrupt input Legend WDDR1 WDR1 RDR1 RPOR1 Write to P1DDR Write to P1DR Read P1DR Read port 1 Note Priority order output compare output PWM output PWM2 output pulse output DR output Figure C 1 e Port 1 Block Diagram Pin P16 ...

Page 1121: ...PWM output enable Output compare output PWM output Pulse output PWM module PWM3 output enable PWM3 output Input capture input External clock input Legend WDDR1 WDR1 RDR1 RPOR1 Write to P1DDR Write to P1DR Read P1DR Read port 1 Note Priority order output compare output PWM output PWM3 output pulse output DR output Figure C 1 f Port 1 Block Diagram Pin P17 ...

Page 1122: ...xD0 IrTxD SCI module Serial transmit enable Serial transmit data Notes 1 Output enable signal 2 Open drain control signal P30DR Reset WODR3 R C Q D P30ODR 1 2 Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 2 a Port 3 Block Diagram Pin P30 ...

Page 1123: ...al receive data enable Serial receive data RxD0 IrRxD P31DR Reset WODR3 R C Q D P31ODR 1 2 Notes 1 Output enable signal 2 Open drain control signal Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 2 b Port 3 Block Diagram Pin P31 ...

Page 1124: ...C1 output enable SDA1 input Interrupt controller IRQ4 interrupt input P32DR Reset WODR3 R C Q D P32ODR 2 3 1 Serial clock input Notes 1 Priority order IIC output Serial clock output DR output 2 Output enable signal 3 Open drain control signal Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 2 c Port 3 Block Diagram Pin P...

Page 1125: ...al transmit data P33DR Reset WODR3 R C Q D P33ODR 1 2 TxD1 IIC1 module SCL1 output IIC1 output enable SCL1 input Notes 1 Output enable signal 2 Open drain control signal Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 2 d Port 3 Block Diagram Pin P33 ...

Page 1126: ... enable Serial receive data enable Serial receive data RxD1 P34DR Reset WODR3 R C Q D P34ODR 1 2 Notes 1 Output enable signal 2 Open drain control signal Priority order IIC output DR output Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 2 e Port 3 Block Diagram Pin P34 ...

Page 1127: ...ial clock output enable Serial clock output Serial clock input enable P35DR Reset WODR3 R C Q D P35ODR 2 3 1 Serial clock input Notes 1 Priority order IIC output Serial clock output DR output 2 Output enable signal 3 Open drain control signal Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 2 f Port 3 Block Diagram Pin P...

Page 1128: ...erial receive data enable Serial receive data RxD4 P36DR Reset WODR3 R C Q D P36ODR 1 2 Notes 1 Output enable signal 2 Open drain control signal Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 2 g Port 3 Block Diagram Pin P36 ...

Page 1129: ...Serial transmit enable Serial transmit data P37DR Reset WODR3 R C Q D P37ODR TxD4 1 2 Notes 1 Output enable signal 2 Open drain control signal Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Figure C 2 h Port 3 Block Diagram Pin P37 ...

Page 1130: ... input Legend RPOR4 Read port 4 n 0 to 5 Figure C 3 a Port 4 Block Diagram Pins P40 to P45 P4n RPOR4 Internal data bus A D converter module Analog input D A converter module Output enable Analog output Legend RPOR4 Read port 4 n 6 or 7 Figure C 3 b Port 4 Block Diagram Pins P46 and P47 ...

Page 1131: ... Mode 4 to 6 Reset WDR7 R P7nDR C Q D P7n RDR7 RPOR7 DMA controller Bus controller Chip select DMA request input 8 bit timer Reset Count input WDDR7 WDR7 RDR7 RPOR7 n 0 or 1 Write to P7DDR Write to P7DR Read P7DR Read port 7 Legend Figure C 4 a Port 7 Block Diagram Pins P70 and P71 ...

Page 1132: ...transferred 8 bit timer Timer output TMO0 Timer output enable IIC module Formatress clock input 1 WDDR7 WDR7 RDR7 RPOR7 Write to P7DDR Write to P7DR Read P7DR Read port 7 Legend Note Priority order Mode7 DMA transfer end output 8 bit timer output DR output Mode4 5 6 Chip select output DMA transfer end output 8 bit timer output DR output Figure C 4 b Port 7 Block Diagram Pin P72 ...

Page 1133: ...r end enable DMA transfer end 8 bit timer Timer output TMO1 Timer output enable 1 WDDR7 WDR7 RDR7 RPOR7 Write to P7DDR Write to P7DR Read P7DR Read port 7 Legend Note Priority order Mode7 DMA transfer end output 8 bit timer output DR output Mode4 5 6 Chip select output DMA transfer end output 8 bit timer output DR output Figure C 4 c Port 7 Block Diagram Pin P73 ...

Page 1134: ...Q D P74 RDR7 RPOR7 8 bit timer 8 bit timer output enable 8 bit timer output System controller Manual reset input enable Manual reset input P74DR WDDR7 WDR7 RDR7 RPOR7 Write to P7DDR Write to P7DR Read P7DR Read port 7 Legend Figure C 4 d Port 7 Block Diagram Pin P74 ...

Page 1135: ...le Timer output enable Serial clock output enable Serial clock input enable Serial clock Timer output Serial clock input WDDR7 WDR7 RDR7 RPOR7 Write to P7DDR Write to P7DR Read P7DR Read port 7 Legend Note Priority order Serial clock output 8 bit timer output DR output Figure C 4 e Port 7 Block Diagram Pin P75 ...

Page 1136: ...ata bus WDDR7 Reset WDR7 R C Q D P76 RDR7 RPOR7 SCI module Serial receive data enable Serial receive data RxD3 P76DR WDDR7 WDR7 RDR7 RPOR7 Write to P7DDR Write to P7DR Read P7DR Read port 7 Legend Figure C 4 f Port 7 Block Diagram Pin P76 ...

Page 1137: ...ta bus WDDR7 Reset WDR7 R C Q D P77 RDR7 RPOR7 SCI module Serial transmit enable data Serial transmit data TxD3 P77DR WDDR7 WDR7 RDR7 RPOR7 Write to P7DDR Write to P7DR Read P7DR Read port 7 Legend Figure C 4 g Port 7 Block Diagram Pin P77 ...

Page 1138: ... input RPOR9 n 0 to 5 Read port 9 Legend Figure C 5 a Port 9 Block Diagram Pins P90 to P95 P9n RPOR9 Internal data bus A D converter module Analog input D A converter module Output enable Analog output RPOR9 n 6 or 7 Read port 9 Legend Figure C 5 b Port 9 Block Diagram Pins P96 and P97 ...

Page 1139: ...Reset WDDRA R C Q D PAnDDR Reset WODRA RPCRA R C Q D PAnODR 1 2 Mode4 5 6 Address enable Notes 1 Output enable signal 2 Open drain control signal WDDRA WDRA WODRA WPCRA RDRA RPORA RODRA RPCRA Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Legend Figure C 6 a Port A Block Diagram Pin PA0 ...

Page 1140: ... TxD output enable WDDRA R C Q D PAnDDR Reset WODRA RPCRA R C Q D PAnODR 1 2 Mode 4 5 6 Address enable Notes 1 Output enable signal 2 Open drain control signal WDDRA WDRA WODRA WPCRA RDRA RPORA RODRA RPCRA Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Legend Figure C 6 b Port A Block Diagram Pin PA1 ...

Page 1141: ... input WDDRA R C Q D PAnDDR Reset WODRA RPCRA R C Q D PAnODR 1 2 Mode 4 5 6 Address enable Notes 1 Output enable signal 2 Open drain control signal WDDRA WDRA WODRA WPCRA RDRA RPORA RODRA RPCRA Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Legend Figure C 6 c Port A Block Diagram Pin PA2 ...

Page 1142: ...ut SCK output enable WDDRA R C Q D PAnDDR Reset WODRA RPCRA R C Q D PAnODR 1 2 Mode 4 5 6 Address enable Notes 1 Output enable signal 2 Open drain control signal WDDRA WDRA WODRA WPCRA RDRA RPORA RODRA RPCRA Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Legend Figure C 6 d Port A Block Diagram Pin PA3 ...

Page 1143: ... enable WDDRB R C Q D PBnDDR Reset WODRB RPCRB R C Q D PBnODR 1 2 Mode 4 5 6 Address enable TPU input Input capture Notes 1 Output enable signal 2 Open drain control signal WDDRB WDRB WODRB WPCRB RDRB RPORB RODRB RPCRB n 0 to 7 Write to PBDDR Write to PBDR Write to PBODR Write to PBPCR Read PBDR Read port B Read PBODR Read PBPCR Legend Figure C 7 Port B Block Diagram Pins PB0 to PB7 ...

Page 1144: ...t WDDRA R C Q D PCnDDR Reset WODRC RPCRC R C Q D PCnODR 1 2 Mode 4 5 Mode 6 Notes 1 Output enable signal 2 Open drain control signal WDDRA WDRA WODRA WPCRA RDRA RPORA RODRA RPCRA n 0 to 5 Write to PCDDR Write to PCDR Write to PCODR Write to PCPCR Read PCDR Read port A Read PCODR Read PCPCR Legend Figure C 8 a Port C Block Diagram Pins PC0 to PC5 ...

Page 1145: ...t WODRC RPCRC R C Q D PCnODR 1 2 Mode 4 5 Mode 6 PWM output PWM output enable Notes 1 Output enable signal 2 Open drain control signal WDDRA WDRA WODRA WPCRA RDRA RPORA RODRA RPCRA n 6 or 7 Write to PCDDR Write to PCDR Write to PCODR Write to PCPCR Read PCDR Read port A Read PCODR Read PCPCR Legend Figure C 8 b Port C Block Diagram Pins PC6 and PC7 ...

Page 1146: ... upper write R C Q D PDn RDRD RPORD PDnDR WDDRD C Q D PDnDDR RPCRD Mode 7 Mode 4 5 6 External address write Reset R External address upper read WDDRD WDRD WPCRD RDRD RPORD RPCRD n 1 to 7 Write to PDDDR Write to PDDR Write to PDPCR Read PDDR Read port D Read PDPCR Legend Figure C 9 Port D Block Diagram Pin PDn ...

Page 1147: ...Reset WDRE R C Q D PEn RDRE RPORE PEnDR WDDRE C Q D PEnDDR RPCRE Mode 7 Mode 4 5 6 External address write Reset R External addres lower read WDDRE WDRE WPCRE RDRE RPORE RPCRE n 1 to 7 Write to PEDDR Write to PEDR Write to PEPCR Read PEDR Read port E Read PEPCR Legend Figure C 10 Port E Block Diagram Pin PEn ...

Page 1148: ...ernal data bus WDDRF Reset WDRF R C Q D PF0 RDRF RPORF Bus request input IRQ interrupt input PF0DR Bus controller BRLE bit Mode 4 5 6 WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 11 a Port F Block Diagram Pin PF0 ...

Page 1149: ...4 5 6 BUZZ output BUZZ output enable Reset WDRF R PF1DR C Q D PF1 RDRF RPORF Bus controller BRLE output Bus request acknowledge output WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 11 b Port F Block Diagram Pin PF1 ...

Page 1150: ...RPORF Bus request output enable Bus request output Wait input LCAS output enable LCASS bit LCAS output Bus controller Wait enable Mode 4 5 6 Mode 4 5 6 Mode 4 5 6 WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 11 c Port F Block Diagram Pin PF2 ...

Page 1151: ...bus WDDRF Reset WDRF R PF3DR C Q D PF3 RDRF RPORF Bus controller ADTRG input IRQ interrupt input LWR output Mode 4 5 6 WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 11 d Port F Block Diagram Pin PF3 ...

Page 1152: ...t Internal data bus Mode 4 5 6 WDDRF Reset WDRF R PF4DR C Q D PF4 RDRF RPORF Bus controller HWR output WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 11 e Port F Block Diagram Pin PF4 ...

Page 1153: ...et Internal data bus WDDRF Reset Mode 4 5 6 WDRF R PF5DR C Q D PF5 RDRF RPORF Bus controller RD output WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 11 f Port F Block Diagram Pin PF5 ...

Page 1154: ...s WDDRF Reset Mode 4 5 6 WDRF R PF6DR C Q D PF6 RDRF RPORF Bus controller LCAS output LCAS output enable LCASS AS output WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 11 g Port F Block Diagram Pin PF6 ...

Page 1155: ...R PF7DR C Q D PF7 RDRF RPORF ø Reset Internal data bus R Mode 4 5 6 S C Q D PF7DDR Note Set priority 1 WDDRF WDRF RDRF RPORF Write to PFDDR Write to PFDR Read PFDR Read port F Legend Figure C 11 h Port F Block Diagram Pin PF7 ...

Page 1156: ...Internal data bus WDDRG Mode 4 5 6 Reset WDRG R PG0DR C Q D PG0 RDRG RPORG Bus controller IRQ interrupt input CAS enable CAS output WDDRG WDRG RDRG RPORG Write to PGDDR Write to PGDR Read PGDR Read port G Legend Figure C 12 a Port G Block Diagram Pin PG0 ...

Page 1157: ...a bus WDDRG Reset Mode 4 5 6 WDRG R PG1DR C Q D PG1 RDRG RPORG Bus controller OE output OE output enable Chip select WDDRG WDRG RDRG RPORG Write to PGDDR Write to PGDR Read PGDR Read port G Legend Figure C 12 b Port G Block Diagram Pin PG1 ...

Page 1158: ...eset WDRG R PGnDR C Q D PGn RDRG RPORG Bus controller Chip select Mode 4 5 6 Internal data bus WDDRG WDRG RDRG RPORG n 2 or 3 Write to PGDDR Write to PGDR Read PGDR Read port G Legend Figure C 12 c Port G Block Diagram Pin PG2 and PG3 ...

Page 1159: ... D PG4 RDRG RPORG Bus controller Chip select Mode 4 5 6 D Reset R Mode 4 5 Mode 6 7 Internal data bus S C Q D PG4DDR WDDRG WDRG RDRG RPORG Write to PGDDR Write to PGDR Read PGDR Read port G Legend Figure C 12 d Port G Block Diagram Pin PG4 ...

Page 1160: ...ut port P73 CS7 P72 CS6 P71 CS5 P70 CS4 7 4 to 6 T T kept kept T T kept DDR OPE 0 T DDR OPE 1 H kept T I O port DDR 0 Input port DDR 1 CS7 to CS4 Port 9 4 to 7 T T T T T Input port Port A 4 5 6 L T kept kept T T Address output OPE 0 T Address output OPE 1 kept Otherwise kept Address output T Otherwise kept Address output A19 to A17 Otherwise I O port 7 T kept T kept kept I O port Port B 4 5 6 L T ...

Page 1161: ... 0 I O port 7 T kept T kept kept I O port Port D 4 to 6 T T T T T Data bus 7 T kept T kept kept I O port Port E 4 to 6 8 bit bus T kept T kept kept I O port 16 bit bus T T T T T Data bus 7 T kept T kept kept I O port PF7 ø 4 to 6 Clock output kept T DDR 0 T DDR 1 H kept DDR 0 T DDR 1 Clock output 7 T kept T DDR 0 T DDR 1 H kept DDR 0 T DDR 1 Clock output PF6 AS LCAS 4 to 6 H H T OPE 0 T LCAS outpu...

Page 1162: ... Otherwise kept LCAS output T BREQOE 1 BREQO WAITE 1 T LCAS output LCAS BREQOE 1 BREQO WAITE 1 WAIT 7 T kept T kept kept I O port PF1 BACK BUZZ 4 to 6 T kept T BRLE 0 BUZZE 0 I O port BRLE 0 BUZZE 1 H BRLE 1 H BRLE 0 BUZZE 0 I O port BRLE 0 BUZZE 1 H BRLE 1 L BRLE 0 BUZZE 0 I O port BRLE 0 BUZZE 1 BUZZ BRLE 1 BACK 7 T kept T kept kept I O port PF0 BREQ IRQ2 4 to 6 T kept T BRLE 0 kept BRLE 1 T T B...

Page 1163: ... 0 Input port OE 0 DDR 1 CS3 OE 1 DDR 1 OE 7 T kept T kept kept I O port PG0 CAS IRQ6 4 to 6 T kept T DRAME 0 kept DRAME 1 OPE 1 CAS DRAME 1 OPE 1 T T DRAME 0 I O port DRAME 1 CAS 7 T kept T kept kept I O port Legend H High level L Low level T High impedance kept Input port becomes high impedance output port retains state DDR Data direction register OPE Output port enable WAITE Wait input enable B...

Page 1164: ... STBY low to RES high 0 ns or more STBY RES t2 0ns t1 10tcyc Figure E 1 Timing of Transition to Hardware Standby Mode 2 To retain RAM contents with the RAME bit cleared to 0 in SYSCR or when RAM contents do not need to be retained RES does not have to be driven low as in 1 Timing of Recovery from Hardware Standby Mode Drive the RES signal low and the NMI signal high approximately 100 ns or more be...

Page 1165: ...33 F ZTAT HD64F2633 HD64F2633F 128 pin QFP FP 128 HD64F2633TE 120 pin TQFP TFP 120 Mask ROM HD6432633 HD6432633F 128 pin QFP FP 128 HD6432633TE 120 pin TQFP TFP 120 H8S 2632 HD6432632 HD6432632F 128 pin QFP FP 128 HD6432632TE 120 pin TQFP TFP 120 H8S 2631 HD6432631 HD6432631F 128 pin QFP FP 128 HD6432631TE 120 pin TQFP TFP 120 Note In the planning stage ...

Page 1166: ...Hitachi Code JEDEC EIAJ Weight reference value TFP 120 Conforms 0 5 g Unit mm Dimension including the plating thickness Base material dimension 16 0 0 2 14 0 07 0 10 0 5 0 1 16 0 0 2 0 4 0 10 0 10 1 20 Max 0 17 0 05 0 8 90 61 1 30 91 120 31 60 M 0 17 0 05 1 0 1 00 1 2 0 15 0 04 0 15 0 04 Figure G 1 TFP 120 Package Dimensions ...

Page 1167: ...t mm Dimension including the plating thickness Base material dimension 0 10 M 20 16 0 0 2 65 38 128 0 5 0 10 1 0 0 5 0 2 3 15 Max 0 10 22 0 0 2 102 64 39 103 1 0 22 0 05 14 0 17 0 05 2 70 0 10 0 15 0 10 0 75 0 75 0 20 0 04 0 15 0 04 Figure G 2 FP 128 Package Dimensions ...

Page 1168: ... December 1998 2nd Edition March 2000 Published by Electronic Devices Sales Marketing Group Semiconductor Integrated Circuits Hitachi Ltd Edited by Technical Documentation Group Hitachi Kodaira Semiconductor Co Ltd Copyright Hitachi Ltd 1998 All rights reserved Printed in Japan ...

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