567
15.2
Register Descriptions
15.2.1
Timer Counter (TCNT)
Bit
:
7
6
5
4
3
2
1
0
Initial value :
0
0
0
0
0
0
0
0
R/W
:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from
H'FF to H'00), either the watchdog timer overflow signal (
WDTOVF
) or an interval timer
interrupt (WOVI) is generated, depending on the mode selected by the WT/
IT
bit in TCSR.
TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared
to 0. It is not initialized in software standby mode.
Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see
section 15.2.5, Notes on Register Access.
15.2.2
Timer Control/Status Register (TCSR)
TCSR0
Bit
:
7
6
5
4
3
2
1
0
OVF
WT/
IT
TME
—
—
CKS2
CKS1
CKS0
Initial value :
0
0
0
1
1
0
0
0
R/W
:
R/(W)
*
R/W
R/W
—
—
R/W
R/W
R/W
Note:
*
Only a 0 can be written, for flag clearing.
TCSR1
Bit
:
7
6
5
4
3
2
1
0
OVF
WT/
IT
TME
PSS
RST/
NMI
CKS2
CKS1
CKS0
Initial value :
0
0
0
0
0
0
0
0
R/W
:
R/(W)
*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
*
Only a 0 can be written, for flag clearing.
