737
•
SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
cyc
, as shown in table 25-11 in section 25,
Electrical Characteristics. Note that the I
2
C bus interface AC timing specifications will not be
met with a system clock frequency of less than 5 MHz.
•
The I
2
C bus interface specification for the SCL rise time t
sr
is under 1000 ns (300 ns for high-
speed mode). In master mode, the I
2
C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If t
sr
(the time for SCL to go from low to V
IH
) exceeds
the time determined by the input clock of the I
2
C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table
below.
Table 18-7 Permissible SCL Rise Time (t
Sr
) Values
Time Indication
IICX
t
cyc
Indication
I
2
C Bus
Specification
(Max.)
ø =
5 MHz
ø =
8 MHz
ø =
10 MHz
ø =
16 MHz
ø =
20 MHz
ø =
25 MHz
0
7.5t
cyc
Standard
mode
1000 ns
1000 ns 937 ns
750 ns 468 ns 375 ns
300 ns
High-speed
mode
300 ns
300 ns
300 ns
300 ns 300 ns 300 ns
300 ns
1
17.5t
cyc
Standard
mode
1000 ns
1000 ns 1000 ns 1000 ns 1000 ns 875 ns
700 ns
High-speed
mode
300 ns
300 ns
300 ns
300 ns 300 ns 300 ns
300 ns
•
The I
2
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I
2
C bus interface SCL and SDA output timing is prescribed by t
Scyc
and t
cyc
, as
shown in table 18-6. However, because of the rise and fall times, the I
2
C bus interface
specifications may not be satisfied at the maximum transfer rate. Table 18-8 shows output
timing calculations for different operating frequencies, including the worst-case influence of
rise and fall times.
t
BUFO
fails to meet the I
2
C bus interface specifications at any frequency. The solution is either
(a) to provide coding to secure the necessary interval (approximately 1 µs) between issuance of
a stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
2
C bus.
t
SCLLO
in high-speed mode and t
STASO
in standard mode fail to satisfy the I
2
C bus interface
specifications for worst-case calculations of t
Sr
/t
Sf
. Possible solutions that should be
