Hitachi H8S/2215 Series, Hardware Manual

Page: 196 / 745

Rev. 3.0, 10/02, page 138 of 686
6.10 Bus Arbitration
This LSI has a bus arbiter that arbitrates bus master operations.
There are three bus masters, the CPU, DMAC, and DTC, which perform read/write operations
when they have possession of the bus. Each bus master requests the bus by means of a bus request
signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by
means of a bus request acknowledge signal. The selected bus master then takes possession of the
bus and begins its operation.
6.10.1 Operation
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master making the request. If there are bus requests from
more than one bus master, the bus request acknowledge signal is sent to the one with the highest
priority. When a bus master receives the bus request acknowledge signal, it takes possession of the
bus until that signal is canceled.
The order of priority of the bus masters is as follows:
(High) DMAC > DTC > CPU (Low)
An internal bus access by an internal bus master, and external bus release, can be executed in
parallel.
In the event of simultaneous external bus release request, and internal bus master external access
request generation, the order of priority is as follows:
(High) External bus release > Internal bus master external access (Low)
6.10.2 Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific times at which each bus master can relinquish the bus.
CPU:
The CPU is the lowest-priority bus master, and if a bus request is received from the DMAC
and DTC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for
transfer of the bus is as follows:
•
The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the operations.
•
If the CPU is in sleep mode, it transfers the bus immediately.