Hitachi H8S/2215 Series, Hardware Manual

Page: 192 / 745

Rev. 3.0, 10/02, page 134 of 686
T
1
;
T
2
T
3
T
1
T
2
T
1
T
2
T
3
T
I
T
1
T
2
Address bus
φ
Bus cycle A
Data bus
Bus cycle B
Long output floating time
Data collision
(a) Idle cycle not inserted
(ICIS0 = 0)
Address bus
Bus cycle A
Data bus
Bus cycle B
(b) Idle cycle inserted
(Initial value ICIS0 = 1)
(area A)
(area B)
(area A)
(area B)
Figure 6.23 Example of Idle Cycle Operation (2)
(3) Relationship between Chip Select
(
CS
CS CS
CS
) Signal and Read
(
RD
RD RD
RD
) Signal
Depending on the system’s load conditions, the
RD
signal may lag behind the
CS
signal. An
example is shown in figure 6.24.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A
RD
signal and the bus cycle B
CS
signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the
RD
and
CS
signals.
In the initial state after reset release, idle cycle insertion (b) is set.
T
1
T
2
T
3
T
1
T
2
T
1
T
2
T
3
T
I
T
1
T
2
Address bus
φ φ
Bus cycle A Bus cycle B
(a) Idle cycle not inserted
(ICIS1 = 0)
Possibility of overlap between
(area B) and
Address bus
Bus cycle A Bus cycle B
(b) Idle cycle inserted
(Initial value ICIS1 = 1)
(area A)
(area B)
(area A)
(area B)
Figure 6.24 Relationship between Chip Select (
CS CS CS CS
) and Read (
RD RD RD RD
)