Hitachi H8S/2215 Series, Hardware Manual

Page: 244 / 745

Rev. 3.0, 10/02, page 186 of 686
Bus release
1 block transfer 1 block transfer
Request clear period
Acceptance resumes Acceptance resumes
Minimum of 2 cycles Minimum of 2 cycles
Request clear period
Request
Request
Transfer
source
Transfer
source
Transfer
destination
Transfer
destination
Idle Idle Idle Read Read Write Dead Dead Write
Address bus
DMA control
Channel
DMA
read DMA
write
Bus
release
DMA
dead
DMA
read DMA
write
Bus
release
[1] [2] [3] [4] [5] [6]
[7]
Acceptance after transfer enabling; the signal low level is sampled on the rising
edge of , and the request is held.
The request is cleared at the next bus break, and activation is started in the DMAC.
Start of DMA cycle.
Acceptance is resumed after the dead cycle is completed.
(As in [1], the
signal low level is sampled on the rising edge of , and the request
is held.)
[1]
[2] [5]
[3] [6]
[4] [7]
Figure 7.21 Example of
DREQ DREQ DREQ DREQ
Level Activated Block Transfer Mode Transfer
DREQ
signal sampling is performed every cycle, with the rising edge of the next
φ
cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the
DREQ
signal low level is sampled while acceptance by means of the
DREQ
pin is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. Acceptance resumes after the end of the dead cycle,
DREQ
signal low level
sampling is performed again, and this operation is repeated until the transfer ends.
Note : The
DREQ
signal of this chip is an internal signal of chip, so it is not output from the pin.
7.4.10 DMAC Multi-Channel Operation
The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 7.9
summarizes the priority order for DMAC channels.