Hitachi H8S/2215 Series, Hardware Manual

Page: 176 / 745

Rev. 3.0, 10/02, page 118 of 686
D15 D8 D7 D0
Upper data bus Lower data bus
Byte size
Word size
1st bus cycle
2nd bus cycle
Longword
size
· Even address
Byte size · Odd address
Figure 6.9 Access Sizes and Data Alignment Control (16-Bit Access Space)
6.6.2 Valid Strobes
Table 6.3 shows the data buses used and valid strobes for the access spaces.
In a read, the
RD
signal is valid without discrimination between the upper and lower halves of the
data bus.
In a write, the
HWR
signal is valid for the upper half of the data bus, and the
LWR
signal for the
lower half.
Table 6.3 Data Buses Used and Valid Strobes
Area
Access
Size Read/
Write
Address Valid Strobe
Upper Data Bus
(D15 to D8) Lower Data Bus
(D7 to D0)
Byte Read –
RD
Valid Invalid 8-bit access
space
Write –
HWR
Hi-Z
Byte Read Even
RD
Valid Invalid
Odd Invalid Valid
Write Even
HWR
Valid Hi-Z
Odd
LWR
Hi-Z Valid
Word Read –
RD
Valid Valid
16-bit access
space
Write –
HWR
,
LWR
Valid Valid
Note: Hi-Z: High impedance.
Invalid: Input state: input value is ignored.