Hitachi C28W40TN, Service Manual

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VIDEO ENCODER
The IC (IC500) used is an Analog Devices ADV7170A type which includes Macrovision capability. It is capable of generating either
PAL or NTSC video with VBI teletext, closed caption (NTSC feature) and WSS insertion. In this application we use the chip in PAL
mode and use the WSS option on scan line 23 to allow televisions which respond to it (including the TV display section of the D8
series receivers) to automatically set the optimum picture size dependent on the transmitted AFD (Active Format Descriptor)
information.
The power supply for the IC is 3.3V, but the output transistor buffers are supplied by a separate analogue 9V line direct from the
IDTV or STB motherboard. The 9V is filtered locally by L500, C500, C521, C525. The IC supply is filtered through L501, C503,
C514.
It is controlled by the I2C bus within the digital module, and the reset is generated by the CPU, common with the AV chip, the pull-
ups are R532, R533 and the series protection resistors are R508 and R510. R509 is fitted to set the I2C address.
R507 is used to set the DAC reference currents to give the correct output amplitude.
The chip uses the main 27MHz clock as a reference to process the incoming video data, this is from the clock buffer IC.
The video input is in 8 bit parallel 4:2:2 form from the AV decoder synchronised to the main 27MHz clock.
The outputs are composite (CVBS), red (R), green (G) and blue (B), which are buffered to the video output port through transistor
buffers (Q500 – Q503, R522, R516, R17, R505, R506, R504, R514, R517, R513, R520, R519, R521). An additional filter (C501,
C518, C519, L502, L503) is used in the composite line to further reduce any possible alias products so that the video would be
suitable for a TV in which digital processing is applied. The video outputs are further filtered at the output pins of PL501 to give
EMC/ESD protection.
The system operates with the PAL encoder in master mode, i.e. it supplies horizontal and vertical sync to the AV decoder.
WSS information is sent to the video encoder by the demux in I2C form to insert into the line 23 of the composite stream. This
information is sent to the IC from the CPU on the I2C bus.
There are data and clock connections to the CPU so that VBI World Standard Teletext (WST) can be supported but this feature is
not currently used.
AUDIO DAC (DIGITAL TO ANALOG CONVERTER)
The IC (IC501) is a Crystal CS4334 type, operated from 5V to give sufficient headroom for a full SCART level audio output without
distortion. The 5V supply is locally decoupled by L505, CC508, C509, C522, C524.
The PCM serial data (ASDATA), sample clock (LRCLK), bit clock (BCLK) and oversampling master clock (A_CLK) are supplied by
the AV decoder IC to the audio DAC.
The outputs are stereo (left/right) audio are filtered by R511, R500, C504, C505 at the output (PL500) to provide some ESD and
interference protection.
There are no control or reset functions on the DAC. The output is through PL500.
EXTERNAL DRAM CONTROLLER (IC700, IC701)
GENERAL
The PCB has provision for an external DRAM controller mapped into the E-BUS. The chip select for this is provided through CI A IC.
This allows for the 16bit wide data bus and 24 bit address bus to control an extra 2MB of EDO DRAM. It uses IC700, IC701and its
associated components, but it is not used at present.
CIRCUIT DESCRIPTION
An Altera device (7128 series) is used for this function, it uses the E-BUS as a main data bus, and a chip select mapped from the CI
A chip. The DRAM supported is a 2MB (1M x 16 bit) EDO DRAM similar to that supported by the main CPU.
It is included to cover future possible requirements but it is not currently used.
JTAG TEST CAPABILITY
The Altera chip used as an external DRAM controller has JTAG test capabilty. It can be configured either as part of a ‘one loop’ or
‘two loop’ test system with some of the other chips on the PCB, more details are given in the ‘JTAG testing’ section later.
IEEE1394 INTERFACE (IC600, IC601)
GENERAL
IEEE1394 is a fast serial bus designed to operate at bitrates of 100MB/s, 200MB/s and 400MB/s. It is capable of driving over
reasonably long cable runs, e.g. between rooms, and is thus seen as a means to run full or partial transport streams to and from
display devices and sources, e.g. digital VCR.
The PCB has provision for a IEEE1394 interface with two socket positions. This requires two Texas Instruments ICs, a link layer
chip mapped into the E-BUS, and a physical layer chip. It is designed to use a chip select provided by Common Interface A IC..
The circuitry required is IC600, IC601 and the associated components.
CIRCUIT DESCRIPTION
Silicon designed by Texas Instruments has been designed in for this function. This is made up of a link layer IC (IC600) which
effectively forms part of the data protocol conversion between the controller/data source (the MPEG CPU) and the physical layer
chip (IC601)which communicates with the outside world through CN601, CN602 to provide a high speed bi-directional serial data
link.
An option for DC isolation is provided in the capacitive interface between these ICs.
This interface is not fitted to the PCBs at present.