Hitachi C28W40TN, Service Manual

Page: 47 / 394

46
AV Section Architecture
The video image can be scaled to either one half or one quarter size in the AV chip if appropriate with suitable interpolation filtering
to remove artifacts as far as possible.
32Mb of SDRAM running at 81MHz is used to build and store the screen image in preparation for sending the data out to the video
encoder at the correct field rate. The 81MHz clock is generated within the AV chip by ‘x3’ PLL, using C114, C115, R107. Since the
PLL is very sensitive to any extraneous signals the local power supply decoupling is provided L100, C116, C125, and the local
ground area is isolated through R113.
The SDRAM controller is a dedicated section of the AV chip. The chip selects, RAS, CAS, data and address lines are generated
synchronously with the 81MHz clock for the 2 memory ICs.
The signal bus carrying the video data to the video encoder contains:
•
8 bit wide video samples
•
OSD signal
•
Horizontal and vertical sync
The video samples are in 4:2:2 format synchronous to the 27MHz main clock, giving a luma (Y) sample rate of 13.5MHz and a rate
of 6.75MHz for the U and V chroma components. The OSD signal is generated by the AV chip indicating the presence of on-screen
graphics, this is not used at present. The horizontal and vertical sync signals are generated by the video encoder and the AV
decoder IC is driven in slave mode, these are both negative going sync signals. The information for the display is structured by the
AV chip in an interlaced format optimised for a normal 5 fields/sec TV display.
The audio over-sampling clock is generated by the audio PLL IC (IC220) and fed into the ACLK_32, ACLK_48 and ACLK_441 pins
of the AV chip. It is used to synchronise the decoding and readout of the audio data to the audio DAC.
The audio data signals are outputted from the AV chip in the form of serial PCM, the bus includes:
•
Serial data - sequential left and right channels (ASDATA)
•
Left/right sample synchronising clock (LRCLK)
•
Sample rate clock (BCLK)
•
Master over-sampling clock (A_CLK)
These signals are sent onto the audio DAC (see later).