Hitachi C28W40TN, Service Manual

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COFDM FRONT-END PCB
This PCB carries:
•
Power supply filtering
•
Tuner
•
COFDM decoder and FEC circuitry
•
RS232 serial communications port
•
V22 bis Modem
POWER SUPPLY FILTERING
This filter field is intended to filter incoming noise from the lines and to prevent noise and EMC components being carried out from
the module to the analogue section.
The power for the whole digital module is connected through this PCB, using a network of ferrite beads, chokes and capacitors. The
input power is through PL801 and PL802, and the filtered output lines are carried to the MPEG PCB on PL803, along with some
control signals from the MPEG PCB. The input and filtered/output power lines are:
Input from analogue section Common Filter
Components Section Used on (PCB) Unique Filter components
5V FB800, C787, C788 Tuner COFDM tuner L801, C801, C802, C803
Modem COFDM tuner R899 (zero ohm link)
MPEG, RS232 MPEG * L805, C785, C786
5V standby L800, C771, C799 Tuner loop-through COFDM tuner None
CI chips MPEG + None
12V FB803, C795, C796 MPEG MPEG L807, C793, C794
Fan External Not used
3V3 FB802, C791, C792 COFDM / FEC COFDM tuner L804, C781, C782
MPEG MPEG * L806, C789, C790
ADC COFDM tuner L808, C779, C780
9V None Tuner COFDM tuner L802, C804, C805
30V None Tuner COFDM tuner R788, R789, R790, C806, C807
‘*’ Indicates further filtering and distribution on the MPEG PCB.
‘+’ Indicates optional linking (R783 / R784) for Common Interface power supply, see text.
TUNER
The tuner includes:
•
UHF loop-through
•
First down-converter
•
Local oscillator and control PLL
•
IF filter and second converter stage
•
AGC control
•
ADC (Analogue to Digital Converter)
•
VCXO (Voltage Controlled Oscillator)
The incoming RF signal is looped back out for linking to a conventional a VCR, set-top box or the analogue TV tuner input. The
loop-through is active and has a separate 5V supply pin which is powered in both normal ‘ON’ and standby modes.
The remaining tuner sections use 5V and 9V power rails, with suitable local decoupling.
The first converter stage converts the incoming signals down so that the selected UHF channel is frequency shifted so that it is
centred within the 8MHz IF band centred around 36MHz..
The local oscillator is controlled by the PLL circuitry internal to the tuner, and the frequency selection made using the I2C bus. This
I2C bus is only gated through to the tuner for commands, which are directly addressed to it. The gating is done by IC820 and the
control signal is generated through the main COFDM IC (IC801)using a port pin. The operation of this pin is controlled through I2C
to the COFDM IC. The local pull-ups for the tuner I2C are R786, R787 and the series protection resistors are internal to the tuner.
The 36 MHz IF signal is filtered to remove the out of band frequency components, frequency shifted again down to 4.572MHz and
sampled at 4 times this frequency in the ADC.
The resolution of the ADC internal to the tuner is 8 bit, and the output from the tuner is a 8 bit wide sampled COFDM signal and the
18.288MHz sampling clock, this clock has been internally filtered to remove some of the faster edges to reduce EMC. Resistors
R884 – R889, R860 and R869, R799 are used to link the parallel data signal inputs to the COFDM IC only if the ADC in the tuner is
used.
This is the normal current build but they should be omitted if an ADC external to the tuner unit is used.
The COFDM decoder IC, using the AFC feedback signal to the tuner module, controls the frequency and phase of the 18.288MHz
clock.
The gain of the IF stage is controlled by the signal from the COFDM IC, with the tuner being responsible for the crossover point and
generating the RF AGC signal which is externally linked to the RF stages.