Embedded Solutions
Page 30
TxAEIntEn when set enables the interrupt based on the TX FIFO Almost Empty flag.
When the interrupt occurs a programmable amount of data can be stored into the FIFO
making for an efficient DMA or burst of writes to load the FIFO.
TxUnderFlowEn when set allows the UnderFlow error status to cause an interrupt to the
host. When cleared the UnderFlow status is still available for polling and will not cause
an interrupt.
TxDataByteOrder when cleared retrieves the first byte received from the D7-0 lane in
the FIFO and PCI bus. D15-8 is second and D31-24 last. If the control bit is set the
order is reversed causing D31-24 to be used for the first byte transmitted and D7-0 for
the 4
th
byte sent per longword. Cleared is standard in PC systems. Set may be
required for BigEndian systems.
TxDataBitOrder when cleared transmits the data D0-D7 from each byte as read from
FIFO based on the TxDataByteOrder setting. With both set to ‘0’ the data will transmit
D0 first D31 last. With the TxDataBitOrder set the data is transmitted D7-D0. With both
order bits set the data will be sent D31 first D0 last.
Please note the start bit, parity bit, and stop/marking states are not affected.
TxClkPolarity When set inverts the clock used by the transmitter. The default ‘0’ setting
uses the rising edge to change and the falling edge stable condition. When set the data
changes on the falling edge and is stable on the rising edge.
TxRegPacket when set causes the transmitter to use the packet definition in the Packet
Register instead of the Packet FIFO. Use this setting with consistent packet lengths –
for example in command and control situations.
TxParitySel is used to control whether odd or even parity is added to each byte
transmitted. 0 = even, 1 = odd.
TxClockDir is used to allow the tranmitter to generate the SendTiming signal instead of
receiving it. 1 = generate SendTiming 0 = use SendTiming. The Arc-210 provides the
clock in normal situations. For loop-back testing or interconnection with alternative HW
the clock can be enabled. PLLA is the clock in use.
TxClockSrc is used to select the PLLA or a divided version of PLLA. Set to ‘0’ for use
with PLLA as programmed. Set to ‘1’ to use with secondary divided PLLA clock signal.
Set to ‘0’ for normal operation.
TxStartBit defines the sense of the Start Bit. When set the start bit will be active high.
When cleared the start bit will be active low.
