Embedded Solutions
Page 12
Address Map
Function
Offset
//
PCIeBiSerialDb37LM9 BASE definitions
#define LM9_BASE_BASE
0x0000 // 0 LM9Base Base control register
#define LM9_BASE_PLL_WRITE
0x0000 // 0 LM9Base Base control register
#define LM9_BASE_PLL_READ
0x0000 // 0 LM9Base base control register
#define LM9_BASE_USER_SWITCH
0x0004 // 1 LM9Base User DIP switch read
#define LM9_BASE_XILINX_REV
0x0004 // 1 LM9Base Xilinx revision read port
#define LM9_BASE_XILINX_DES
0x0004 // 1 LM9Base Xilinx design read port
#define LM9_BASE_STATUS
0x0008 // 2 LM9Base status Register offset
// 17-6 IO numbering, 11-0 register numbering for a 12 bit GPIO interface with an IO offset
#define LM9_BASE_GPIO_TERM
0x0040 // 16 LM9Base GPIO Termination Register offset
#define LM9_BASE_GPIO_DIR
0x0044 // 17 LM9Base GPIO Direction Register offset
#define LM9_BASE_GPIO_DATA
0x0048 // 18 LM9Base GPIO Data Register offset --
register data R/W
#define LM9_BASE_GPIO_IO
0x004C // 19 LM9Base GPIO Data IO offset (read only)
Figure 3 PCIeBiSerialDb37LM9 Internal Address Map Base Functions
The address map provided is for the local decoding performed within
PcieBiserialDb37Lm9. The addresses are all offsets from a base address. Dynamic
Engineering prefers a long-word oriented approach because it is more consistent across
platforms.
The map is presented with the #define style to allow cutting and pasting into many
compilers “include” files.
The host system will search the PCI bus to find the assets installed during power-on
initialization. The VendorId = 0x10EE and the CardId = 0x003E for the
PcieBiSerialDb37Lm9.
The LM9 design has 1 channel implemented at this time. The BASE contains the
common elements of the design, while the Channels have the IO specific interfaces.
The BASE starts at the card offset. Channel 0 starts at register 20
Section Register Address Range COM name
(starting Hex address)
Base
0-19 (0x0000)
PLL, Switch, Status
Channel 0
20-39 (0x0050)
ARC-210 Transmitter & Receiver
