Embedded Solutions
Page 16
Base Register Definitions
LM9_BASE_BASE
[$00 Base Control Register Port read/write]
DATA BIT
DESCRIPTION
31-21
spare
20
bit 19 read-back of pll_dat register bit
19
pll_dat [write to PLL, read-back from PLL]
18
pll_s2
17
pll_sclk
16
pll_en
15-0
spare
Figure 5 PcieBiSerialDb37Lm9 Control Base Register Bit Map
This is the base control register for the LM9. The features common to all channels are
controlled from this port. Unused bits are reserved for additional new features. Unused
bits should be programmed ‘0’ to allow for future commonality.
pll_en: When this bit is set to a one, the signals used to program and read the PLL are
enabled.
pll_sclk/pll_dat : These signals are used to program the PLL over the I
2
C serial
interface. Sclk is always an output whereas Sdata is bi-directional. This register is
where the Sdata output value is specified or read-back.
pll_s2: This is an additional control line to the PLL that can be used to select additional
pre-programmed frequencies. Set to ‘0’ for most applications.
The PLL is programmed with the output file generated by the Cypress PLL
programming tool. [CY3672 R3.01 Programming Kit or CyberClocks R3.20.00 Cypress
may update the revision from time to time.] The .JED file is used by the Dynamic Driver
to program the PLL. Programming the PLL is fairly involved and beyond the scope of
this manual. For clients writing their own drivers it is suggested to get the Engineering
Kit for this board including software, and to use the translation and programming files
ported to your environment. This procedure will save you a lot of time. For those who
want to do it themselves the Cypress PLL in use is the 22393. The output file from the
Cypress tool can be passed directly to the Dynamic Driver [Linux or Windows] and used
to program the PLL without user intervention.
