Embedded Solutions
Page 28
LM9_CHAN_TX_AMT_LVL
[0x14] Tx almost-empty level (read/write)
Tx Almost-Full Level Register
Data Bit
Description
31-16
Spare
15-0
Tx FIFO Almost-Empty Level
Figure 15 PcieBiSerialDb37Lm9 TX ALMOST EMPTY LEVEL register
This read/write port accesses the almost-empty level register. When the number of
data words in the transmit data FIFO is less than than this value, the almost-empty
status bit will be set. The register is R/W for 16 bits. The mask is valid for a size
matching the depth of the FIFO.
LM9_CHAN_RX_AFL_LVL
[0x18] Rx almost-full (read/write)
Rx Almost-Full Level Register
Data Bit
Description
31-16
Spare
15-0
Rx FIFO Almost-Full Level
Figure 16 PcieBiSerialDb37Lm9 RX ALMOST FULL LEVEL register
This read/write port accesses the almost-full level register. When the number of data
words in the receive data FIFO is equal or greater than this value, the almost-full status
bit will be set. The register is R/W for 16 bits. The mask is valid for a size matching the
depth of the FIFO. The level includes the pipeline for an additional 4 locations.
