Embedded Solutions
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Please note that RxStartBit and RxMarkingBit should have opposite definitions. The
default for the Arc-210 is Start = ‘1’ and Marking = ‘0’.
LM9_CHAN_RX_PACKET_LEN_FIFO
[0x38] RX Packet size
RX Packet Data Count Port
Data Bit
Description
31-0
RX Data Bytes per Packet Received
Figure 21 PcieBiSerialDb37Lm9 RX Packet Size
This read only port holds the packet size definitions. Each word loaded into the FIFO
represents the size of a Packet loaded into the data FIFO. Please note that this is a
FIFO. The Packet data read will match the Packet Definitions – same order. The data,
once read by the system is no longer available to be read from the FIFO.
LM9_CHAN_RX_TIMEOUT_LEN
[0x3C] RX TimeOut Length
RX TimeOut Port
Data Bit
Description
31-0
Max Clocks before new Packet
Figure 22 PcieBiSerialDb37Lm9 RX TimeOut Length
This read-write only port holds the packet timeout length definition. If the gap between
received bytes is longer than the TimeOut length * 30nS the end of the packet will be
declared [in HW]. When the end of the packet is declared the HW will load the last data
into the FIFO [if needed and resume looking for more data. The packet FIFO will be
updated with the size of the packet received.
The clock used is the PCI clock.
If the Transmitter is running at 1 MHz and has a typical 2 Marking states between bytes
sent then there are 3 uS [Stop, marking, marking]. If there is a defined gap between
packets for a packet break that time can be used. If there is no definition then the
