Embedded Solutions
Page 8
The number of bytes to send is programmable. The number can be stored into a
secondary FIFO to allow multiple packets to be transmitted from a single larger DMA
transfer. The number of bytes can also be stored into a register to cover cases where
the size of each packet is consistent.
The hardware waits until there is a definition of the byte count, and data in the transmit
FIFO before starting. Once started if the data FIFO is empty when the transmitter is
ready to read the next data set an error for underflow is flagged. The error can cause
an interrupt if desired.
The receiver is designed to be always ready when the radio transmits data to the LM9
interface. The receiver channel when enabled can accept data from the radio
independent of the transmitter. This allows for loop-back or other applications. The
ARC-210 can only transmit or receive and not both at the same time. The receiver will
only receive data when the transmitter is not operating – in a system situation.
The receiver uses a 33 MHz clock to sample the received data and clock and to control
the data flow internally. The expected ReceiveTiming rate is around 1 MHz. leaving
plenty of headroom for the sampling and data control.
The received timing input is converted to a series of 33 MHz. pulses which are used to
enable the receive shift register to capture the synchronized Receive Data. As the data
is captured the marking state is checked to allow for initial start-up [10 bits+ of marking
bits in a row]. The state-machines check if in the marking state and then if a start bit
has been received. Data bits are counted and when a complete Start Byte Parity
sequence is received the data is parallel loaded to a holding register. Parity is
calculated and tested against what was received. The data is moved to a secondary
holding register to build up to a 32 bit word. When 4 bytes are received or at the end of
a programmed length the data is moved to the output FIFO.
Both the transmitter and receiver allow for bit and byte reversal. The data is stored as
32 bit words into the transmit FIFO from the system or the receive FIFO from the
interface. The data is used with little Endian conventions as the default – 0,1,2,3 for the
byte order where 0 = D7-0 [data on AD7-0] first and D31-24 last. The bits are sent LSB
first so D0 is first on the line and D31 is last if all 4 bytes are to be sent. Similarly the
receiver loads 0,1,2,3 so the first bit in goes into D0 and the last into D31 for each long
word. When the bytes are reversed the order becomes 3,2,1,0 which which would
make the IO 24 first, 7 last since it is still lsb first. The bit reversal swaps D7 with D0 etc
on each byte read so the order becomes D31 first and D0 last if both reversal options
are selected. For systems using Windows Little Endian is consistent with the driver and
memory mapping. With Linux and some RISC based systems the reversal may be
necessary.
