Dynamic Engineering PCIeBiSerialDb37-LM9, User Manual

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Embedded Solutions Page 21
LM9_CHAN_STATUS
[0x4] Channel Status Read/Clear Latch Write Port
Channel Status Register
Data Bit Description
31 Interrupt Status
30 LocalInt
29-28 Spare
27 RxPacketFull
26 RxPacketMt
25 TxPacketFull
24 TxPacketMt
23 BurstInIdle
22 BurstOutIdle
21 TxIdleState
20 RxIdleState
19 TxFifoUnFlLat
18 RxFifoOvFlLat
17 RxPacketCompletedLat
16 TxPacketCompletedLat
15 Read DMA Interrupt Occurred
14 Write DMA Interrupt Occurred
13 Read DMA Error Occurred
12 Write DMA Error Occurred
11 RxAFLvlIntLat
10 TxAELvlIntLat
9 RxParityErrorLat
8 spare
7 spare
6 Rx FIFO Full
5 Rx FIFO Almost Full
4 Rx FIFO Empty
3 Spare
2 Tx FIFO Full
1 Tx FIFO Almost Empty
0 Tx FIFO Empty
Figure 9 PcieBiSerialDb37Lm9 Channel STATUS PORT
LM9 FIFO: Two 4K x 32 FIFO’s are used to create the internal Tx and Rx memory. The
status for the Tx FIFO and Rx FIFO refer to these FIFO’s. The status is active high.
0x13 would correspond to empty Rx and empty Tx internal FIFO’s.