Embedded Solutions
Page 22
Please note with the Rx side status; the status reflects the state of the FIFO and does
not take the 4 deep pipeline into account. For example the FIFO may be empty and
there may be valid data within the pipeline. The data count with the combined FIFO and
pipeline value and can also be used for read size control. [see later in register
descriptions]
In addition there are two Packet FIFO’s to store the Packet Lengths. The empty and full
status for each FIFO is provided. When neither is set, there is data in the FIFO and
room for more.
Rx FIFO Empty: When a one is read, the FIFO contains no data; when a zero is read,
there is at least one data word in the FIFO.
Rx FIFO Almost Full: When a one is read, the number of data words in the data FIFO is
greater than the value written to the corresponding RX_AFL_LVL register; when a zero
is read, the FIFO level is less than that value.
Rx FIFO Full: When a one is read, the receive data FIFO is full; when a zero is read,
there is room for at least one more data-word in the FIFO. If the FIFO is full when time
to write received data to the FIFO an overflow error is declared.
Tx FIFO Empty: When a one is read, the FIFO contains no data; when a zero is read,
there is at least one data word in the FIFO. If the FIFO is empty when time to read
transmitted data from the FIFO an underflow error is declared.
Tx FIFO Almost Empty: When a one is read, the number of data words in the data FIFO
is less than or equal to the value written to the corresponding TX_AMT_LVL register;
when a zero is read, the FIFO level is more than that value.
Tx FIFO Full: When a one is read, the transmit data FIFO is full; when a zero is read,
there is room for at least one more data-word in the FIFO.
RxFifoOvFlLat: When a one is read, an error has been detected. This will occur if FIFO
is full when the loader function tries to write to it. A zero indicates that no error has
occurred. This bit is latched and can be cleared by writing back to the Status register
with a one in the appropriate bit position.
RxParityErrorLat: When a one is read, an error has been detected. This will occur if
incorrect parity is received. The exact location of the error is not known. It is
recommended that the error bits are cleared per packet to allow the system to
retransmit the packet with the error. This bit is latched and can be cleared by writing
back to the Status register with a one in the appropriate bit position.
