Embedded Solutions
Page 9
The transmitter and receiver have 4K x 32 FIFO’s with direct access, DMA support, and
loop-back capabilities. The driver/reference software includes examples of all three
modes.
DMA when used will keep the transmitter FIFO full and the receiver FIFO empty
automatically and without overflow etc. The hardware has the necessary flow control
designed in.
In addition the transmitter side has a 2K x 32 Packet FIFO where each entry stored
represents the number of bytes to send in a given transmission. RTS is held on during
a packet transmission. RTS is released between transmissions and then reasserted
and checked. CTS is not checked during the transmission since the radio is
unidirectional and has no way to receive a “pause” from the “other end”. Smaller
packets can be used for more frequent checking.
For situations where more consistent and likely shorter transmissions are to happen the
registered byte count can be used. The hardware will repeat the same size packet with
new data from the data FIFO as long as there is data in the FIFO.
Please note that the Data in the FIFO’s are packed on a Packet basis. The last LW is
padded as necessary to reach 32 bits. On the receive side the storage register is
cleared between each long word to pad with 0’s in each location not used.
Similarly the RX Packet FIFO is used to store the number if bytes in each packet
received. The RX Packet FIFO is also 2K x 32.
The receive Packet size can be determined by programming the local Packet Length
and selection of the Packet length mode or by using the timeout function and having a
variable length packet automatically received.
Custom cables can be manufactured to your requirements. The loop-back IO
definitions are toward the end of this manual. Please contact Dynamic Engineering with
your specifications.
In the “LM9” design the Termination and Direction controls are set in the VHDL for the
ARC-210 IO and programmable with software for the GPIO. The received signals are
terminated and the transmitted signals are not.
All of the IO are routed through the FPGA to allow for custom applications. Larger
external and internal FIFO’s and Dual Ported memories can be implemented with
different FPGA selections and adding the 128K x 32 FIFO’s to the board.
