Embedded Solutions
Page 31
TxMarkingBit defines the sense of the Stop Bits and Marking State. When cleared the
bits following the parity bit leading up to the start bit will be ‘0’.
Please note that TxStartBit and TxMarkingBit should have opposite definitions. The
default for the Arc-210 is Start = ‘1’ and Marking = ‘0’.
ClkDiv is used to define the secondary divisor option. The counter uses the
programmed value to compare against before changing sense. The counter advances
from 0 to the programmed count for N+1. The signal changes sense 2x per period for a
factor of 2. The division is therefore 2*(n+1).
Until more channels are added to this design the ClkDiv and TxClkSrc should be treated
as reserved. Extremely low frequencies below the PLL capability would be the
exception. In this case a 1 MHz or similar frequency can be programmed into the PLL
and the divisor used to reach lower frequencies.
LM9_CHAN_TX_PACKET_LEN_FIFO
[0x20] TX Packet Size FIFO
TX Data Count Port
Data Bit
Description
31-0
TX Data Bytes per Packet
Figure 18 PcieBiSerialDb37Lm9 TX Packet Size FIFO
The TX Packet FIFO can store multiple Packet size definitions. Packet Data can be
transferred via DMA from host memory to the TX Data FIFO and the corresponding
definitions stored into this FIFO. 2K x 32 is the FIFO size.
Larger DMA transfers can be used for grouped packets and individual packets sent if
the data needs to be parsed. See status register for information on underflow. Please
see the REG version if the packet size is consistent.
This port is read-write. Reading back will remove the data from the FIFO. The read
path is provided for self test purposes.
