Embedded Solutions
Page 13
Function
Offset from Channel Base Address
//
PCIeBiSerialDb37LM9 Channel definitions
#define LM9_CHAN_CNTRL
0x00000000 //0 LM9Chan General control register
#define LM9_CHAN_STATUS
0x00000004 //1 LM9Chan Interrupt status port
#define LM9_CHAN_INT_CLEAR
0x00000004 //1 LM9Chan Interrupt clear port
#define LM9_CHAN_WR_DMA_PNTR
0x00000008 //2 LM9Chan Write DMA dpr physical PCI
address register
#define LM9_CHAN_TX_FIFO_COUNT
0x00000008 //2 LM9Chan TX FIFO count read port
#define LM9_CHAN_RD_DMA_PNTR
0x0000000C //3 LM9Chan Read DMA physical PCI
address register
#define LM9_CHAN_RX_FIFO_COUNT
0x0000000C //3 LM9Chan RX FIFO count read port
including pipeline
#define LM9_CHAN_FIFO
0x00000010 //4 LM9Chan FIFO for single word RW
#define LM9_CHAN_TX_AMT_LVL
0x00000014 //5 LM9Chan TX almost empty level RW
#define LM9_CHAN_RX_AFL_LVL
0x00000018 //6 LM9Chan RX almost full level register
RW, used for HW control
#define LM9_CHAN_TX
0x0000001C //7 LM9Chan TX control register
#define LM9_CHAN_TX_PACKET_LEN_FIFO 0x00000020 //8 LM9Chan Packet Length Tx FIFO
#define LM9_CHAN_TX_PACKET_LEN_REG 0x00000024 //9 LM9Chan Packet Length Tx Register
#define LM9_CHAN_RX
0x00000034 //13 LM9Chan RX control register
#define LM9_CHAN_RX_PACKET_LEN_FIFO 0x00000038 //14 LM9Chan Packet Length Rx FIFO
#define LM9_CHAN_RX_TIMEOUT_LEN
0x0000003C //15 LM9Chan Time out between packets
#define LM9_CHAN_RX_BYTECOUNT_LEN
0x00000040 //16 LM9Chan Byte Count length expected
Figure 4 PcieBiSerialDb37Lm9 Channel Address Map
