3.0 Electrical Interfaces
Fusion 878A
3.3 General Purpose I/O Port
PCI Video Decoder
3-14
Conexant
100600B
illustrates SPI output clock-data timing information. The falling
edge of the output GPCLK triggers the change in video data. This should allow
for ample setup and hold times for any device accepting the data.
Table 3-3. SPI GPIO Output Signals
GPIO
Signal
Description
Pin
Number
[23]
HRESET
A 64-clock-long active low pulse, output following the rising edge of CLKx1. The
falling edge of HRESET indicates the beginning of a new video line.
56
[22]
VRESET
An active low signal that is at least two lines long (for non-VCR sources, VRESET is
normally six lines long). It is output following the rising edge of CLKx1. The falling
edge of VRESET indicates the beginning of a new field of video output. The falling
edge of VRESET lags the falling edge of HRESET by two clock cycles at the start of an
odd field. At the start of even fields, the falling edge of VRESET is in the middle of a
scan line, horizontal count (HPIXEL/2)+1, on scan line 263 for NTSC and scan line
313 for PAL.
57
[21]
HACTIVE
An active high signal that indicates the beginning of the active video and is output
following the rising edge of CLKx1. The HACTIVE flag is used to indicate where
nonblanking pixels are present. The start and the end of the HACTIVE signal can be
adjusted by programming the HDELAY and HACTIVE registers.
58
[20]
DVALID
An active high pixel qualifier that indicates whether or not the associated pixel is
valid. DVALID is independent of the HACTIVE and VACTIVE signals. DVALID indicates
which pixels are valid. DVALID will toggle high outside of the active window,
indicating a valid pixel outside the programmed active region.
59
[19]
CBFLAG
An active high pulse that indicates when Cb data is being output on the chroma
stream. During invalid pixels, CBFLAG holds the value of the last valid pixel.
60
[18]
FIELD
When high, indicates that an even field (field 2) is being output; when low it indicates
that an odd field (field 1) is being output. The transition of FIELD is synchronous with
the end of active video (i.e. the trailing edge of ACTIVE). The same information can
also be derived by latching the HRESET signal with VRESET.
61
[17]
VACTIVE
An active high signal that indicates the beginning of the active video and is output
following the rising edge of CLKx1. The VACTIVE flag is used to indicate where
nonblanking pixels are present. The start and the end of the VACTIVE signal can be
adjusted by programming the VDELAY and VACTIVE registers.
67
[16]
VBISEL
An active high signal that indicates the beginning and end of the VBI. The end of
VBISEL will adjust accordingly when VDELAY is changed.
68
[15:8]
Y[7:0]
Digital pins for the luminance component of the video data stream.
72–69,
78–75
[7:0]
CrCb[7:0]
Digital pins for the chrominance component of the video data stream.
79–86
