5.0 Control Register Definitions-Function 0
Fusion 878A
5.3 Local Registers (Memory Mapped)
PCI Video Decoder
5-30
Conexant
100600B
0x0E0—VBI Packet Size Register (VBI_PACK_SIZE)
0x0E4—VBI Packet Size / Delay Register (VBI_PACK_DEL)
0x0E8—Field Capture Counter Register (FCAP)
Upon reset FCAP is initialized to 00.
0x0F0—PLL Reference Multiplier Register (PLL_F_LO)
Upon reset this register is initialized to 00.
0x0F4—PLL Reference Multiplier Register (PLL_F_HI)
Upon reset this register is initialized to 00.
Bits
Type
Default
Name
Description
[7:0]
RW
0x00
VBI_PKT_LO
Lower 8 bits for the number of raw data DWORDS (four 8-bit samples) to
capture while in VBI capture mode.
Bits
Type
Default
Name
Description
[7:2]
RW
000000
VBI_HDELAY
The number of CLKx1’s to delay from the trailing edge of HRESET before
starting VBI line capture.
[1]
RW
0
EXT_FRAME
A value of 1 extends the frame output capture region to include the 10 lines
prior to the default VACTIVE region.
[0]
RW
0
VBI_PKT_HI
Upper bit for the number of raw data DWORDS (four 8-bit samples) to capture
while in VBI capture mode.
Bits
Type
Default
Name
Description
[7:0]
RW
(1)
0x00
FCNTR
Counts field transitions when any CAPTURE bit is set.
NOTE(S):
(1)
Any write to this register resets the contents to 0.
Bits
Type
Default
Name
Description
[7:0]
RW
0x00
PLL_F_LO
Lower byte of PLL Frequency register.
Bits
Type
Default
Name
Description
[7:0]
RW
0x00
PLL_F_HI
Upper byte of PLL Frequency register.
