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5.0 Control Register Definitions-Function 0
The Fusion 878A supports two types of address spaces: Function 0 and Function 1. This chapter defines
Function 0. The configuration address space includes the predefined PCI configuration registers. The memory
address space includes all the local registers used by CN878A to control the remaining portions of the device.
Both the PCI configuration address space and the memory address space start at memory location 0x00. The
PCI-based system distinguishes the two address spaces based on the Initialization Device Select, PCI address,
and command signals that are issued during the appropriate software commands.
5.1 PCI Configuration Space
The PCI configuration space defines the registers used to interface between the host and the PCI local bus.
Since the Fusion 878A is a multifunctional device, it operates within two function definitions during a
configuration type 0 transaction. Function 0 responds as a multimedia video device. Each function has its own
address space. AD[10:8] indicates which function the PCI bus is addressing. AD[10:8] = 000 specifies Function
0. The register definitions in this chapter apply only to Function 0.
The configuration space registers are stored in DWORDs and defined by byte addresses. Therefore, a register
one byte in length can have a bit definition other than [7:0] (for example [31:24]), depending on its location in
the configuration space. For a discussion on configuration cycle addressing, refer to
PCI Local Bus
Specification, Revision 2.2
.
The configuration space is accessible at all times even though it is not typically accessed during normal
operation. These registers are normally accessed by the Power On Self Test (POST) code and by the device
driver during initialization time. Software will, however, read the status register during normal operation when a
PCI bus error occurs and is detected by Fusion 878A.
The configuration space is accessed when the IDSEL pin is high, and AD[1:0] equals 00; otherwise, the
cycle is ignored. The configuration register addresses are each offset by four, since AD[1:0] equals 00.
Fusion 878A supports burst R/W cycles. Write operations to reserved, unimplemented, or read-only
registers/bits complete normally with the data discarded. Read accesses to reserved or unimplemented
registers/bits return a data value equal to 0.
Internal addressing of Fusion 878A registers occurs via AD[7:2] and the byte enable bits of the PCI bus. The
8-bit byte address for each of the following register locations is {AD[7:2], 00}.
CardBus CIS Pointer registers are not implemented in the Fusion 878A. User-definable features, BIST,
Cache Line Size, and Expansion ROM Base Address register also are not supported.
This section defines the organization of the registers within the 64-byte predefined header portion of the
illustrates the configuration space header. For details on the PCI bus, refer to
the
PCI Local Bus Specification, Revision 2.2
.
