3.0 Electrical Interfaces
Fusion 878A
3.1 Input Interface
PCI Video Decoder
3-4
Conexant
100600B
This clock is used to generate the CLKx2 frequency via the following
equation:
These values should be programmed as follows to generate PAL frequencies:
The PLL can be put into low power mode by setting PLL_I to 0. For NTSC
operation, PLL_I should be set to 0 to disable PLL. In this mode, the correct clock
frequency is already input to the system, and the PLL is shut down. An
out-of-lock or error condition is indicated by the PLOCK bit in the DSTATUS
register.
When using the PLL to generate the required NTSC and PAL clock
frequencies, the following sequence must be followed:
1.
Initially, TGCKI bits in the TGCTRL register must be programmed for
normal operation of the XTAL ports.
2.
After the PLL registers are programmed, the PLOCK bit in the DSTATUS
register must be polled until it has been verified that the PLL has attained
lock (approximately 500 ms).
3.
At that point the TGCKI bits are set to select operation via the PLL.
Crystals are specified as follows:
•
28.63636 MHz
•
Third overtone or fundamental
•
Parallel resonant
•
30 pF load capacitance
•
50 ppm
•
Series resistance 40
Ω
or less
Recommended crystals for use with the Fusion 878A are listed in
Frequency = (F_input
÷
PLL_X) × PLL_I.PLL_F
÷
PLL_C
where
F_input = 28.63636 MHz (50 ppm)
PLL_X = Reference pre-divider (divide by 2)
PLL_I =
Integer
input
PLL_F =
Fractional
input
PLL_C
= Post divider (divide by 6)
PAL (CLKx2 = 35.46895 MHz)
PLL_X = 1
PLL_I = 0x0E
PLL_F = 0xDCF9
PLL_C = 0
