5.0 Control Register Definitions-Function 0
Fusion 878A
5.3 Local Registers (Memory Mapped)
PCI Video Decoder
5-24
Conexant
100600B
Video Timing Control Register
0x6C—Even Field (E_VTC)
0xEC—Odd Field (O_VTC)
Upon reset, this register is initialized to 0x00. VFILT(0) is the LSB.
0x07C—Software Reset Register (SRESET)
This command register can be written at any time. Read cycles to this register return an undefined value. A data
write cycle to this register resets the video decoder and scaler registers to the default state. Writing any data
value into this address resets the device.
Bits
Type
Default
Name
Description
[7]
RW
0
HSFMT [7:6]
00 = 64
01 = 48
10 = 32
11 = 16
This bit selects between a 32-clock-wide HRESET and the standard
64-clock-wide HRESET.
0 = HRESET is 64 CLKx1 cycles wide
1 = HRESET is 32 CLKx1 cycles wide
[6:3]
Reserved
These bits should be written only with a logical 0.
[2:0]
RW
000
VFILT
These bits control the number of taps in the Vertical Scaling Filter. Choose the
number of taps in conjunction with the horizontal scale factor to ensure that
the needed data does not overflow the internal FIFO.
000*= 2-tap interpolation only.
(1)
001 = 2-tap
and 2-tap interpolation.
(2)
010 = 3-tap
and 2-tap interpolation.
(3)
011 = 4-tap
and 2-tap interpolation.
(3)
100*= 2-tap
(1)
101 = 3-tap
(2)
110 = 4-tap
(3)
111 = 5-tap
(3)
NOTE(S):
(1)
Available at all resolutions.
(2)
Only available if scaling to less than 385 horizontal active pixels (CIF or smaller).
(3)
Only available if scaling to less than 193 horizontal active pixels (QCIF or smaller).
1
2
--- 1
Z
1
–
+
(
)
1
4
--- 1
2
Z
1
–
Z
2
–
+
+
(
)
1
8
--- 1
3
Z
1
–
3
Z
2
–
Z
3
–
+
+
+
(
)
1
2
--- 1
Z
1
–
+
(
)
1
4
--- 1
2
Z
1
–
Z
2
–
+
+
(
)
1
8
--- 1
3
Z
1
–
3
Z
2
–
Z
3
–
+
+
+
(
)
1
16
------ 1
4
Z
1
–
6
Z
2
–
4
Z
3
–
Z
4
–
+
+
+
+
(
)
