2/24/2008 9T6WP
BCM7405
Preliminary Hardware Data Module
06/29/07
Bro a d c o m C o rp o r a ti o n
Page xii
Document
7405-1HDM00-R
Figure 1-33: Soft Modem Connections ..........................................................................................................1-91
Figure 1-34: Power-Up Sequence Waveforms Without On-chip Voltage Regulator......................................1-94
Figure 1-35: Data Transport Input Band Timing ..........................................................................................1-150
Figure 1-36: MPOD Input Timing .................................................................................................................1-151
Figure 1-37: RMX Serial Output Port Timing (Clock/Data/Sync Mode) .......................................................1-152
Figure 1-38: MPOD Output Timing ..............................................................................................................1-153
Figure 1-39: I2S Audio/Compressed I2S Output Timing Diagram ...............................................................1-154
Figure 1-40: SPDIF Audio Output Timing Diagram......................................................................................1-155
Figure 1-41: DAC Audio Output Timing Diagram.........................................................................................1-156
Figure 1-42: 256Fs Audio Clock Output Timing Diagram ............................................................................1-157
Figure 1-43: PCI Interface Timing Diagram .................................................................................................1-158
Figure 1-44: Async Read Timing Diagram ...................................................................................................1-159
Figure 1-45: Async Write Timing Diagram ...................................................................................................1-160
Figure 1-46: Synchronous Read Timing Diagram........................................................................................1-161
Figure 1-47: Synchronous Write Timing Diagram ........................................................................................1-162
Figure 1-48: Write Cycle Timing ..................................................................................................................1-163
Figure 1-49: Read Cycle Timing ..................................................................................................................1-163
Figure 1-50: Clock-to-Data Timing ...............................................................................................................1-165
Figure 1-51: ITU656 Output Timing Diagram...............................................................................................1-166
Figure 1-52: Serial Teletext Port Output Timing Diagram ............................................................................1-167
Figure 1-53: Example: Vendor (TXC) Part Number for 3OT Crystal: 7EA0000023 .....................................1-170
Figure 1-54: 976-FCBGA+HS Package (With Heat Sink)............................................................................1-176
Figure 1-55: 976-FCBGA+HS Package (Without Heat Sink).......................................................................1-177
