2/24/2008 9T6WP
BCM7405
Preliminary Hardware Data Module
Functional Description
06/29/07
Bro a d c o m C o rp o r a ti o n
Page 1-84
Peripherals
Document
7405-1HDM00-R
PCI
AND
E
XTERNAL
B
US
I
NTERFACE
The BCM7405 includes a shared interface that supports 33 MHz PCI 2.3 and external buses to allow the internal processor
control of external peripherals that may be attached to the PCI bus and to allow an external controller to access the
peripherals and memory associated with the BCM7405.
The PCI and EBI interfaces share many of the same pins to reduce the overall pin counts. Both PCI and EBI operate at the
same PCI clock input frequency. Critical control signals such as FRAMEb and CSb are not shared. The arbitration and
multiplexing of this PCI/EBI interface happens completely in hardware. When the interface is operated as an EBI function,
PCI devices will not respond because the FRAMEb is not asserted. When the interface is operated as a PCI function, EBI
devices will not respond because the CSb is not asserted. Both EBI and PCI interfaces operate at a max clock frequency of
33 MHz.
Software running on the internal MIPS processor can allow the BCM7405 to act as a PCI South bridge. This allows an easier
migration path for external processors to access the peripheral devices (such as the USB controller).
When in PCI Client mode, the EBI function is disabled and the PCI interface supports both internal and external PCI masters.
When in PCI Host Bridge mode, the EBI interface functions as an EBI bus master only. It supports asynchronous,
synchronous and 68K modes. The PCI interface supports both external and internal PCI masters. The internal PCI arbiter
is designed to support the EBI request as a modified PCI master with special request and grant handshaking. If an external
PCI arbiter is selected, the special EBI request/grant pair maps to the PCI GNT2b/REQ2b pins.
The EBI is an external bus interface intended to support the connection of external SRAMS, flash memories, and EPROMS,
and to interface with additional external peripherals. It is compatible with the 68000 bus definition.
The BCM7405 EBI provides a 27-bit address bus and a 16-bit bidirectional data bus. In addition, separate read and write
strobes are provided along with up to six firmware-configurable chip select signals. Each chip select is fully programmable
and:
•
Supports block sizes between 8 KB and 64 MB
•
Has extended clock cycle access control
•
Has 8-bit or 16-bit selection of peripheral data bus width
The BCM7405 EBI automatically breaks up accesses where the transfer data is larger than the target size, such as a 32-bit
read or write initiated by the CPU or internal DMA targeting an 8-bit wide peripheral results in four separate byte-wire read
or write accesses to the target.
The BCM7405 EBI supports glueless connection to an external Nand Flash device for booting the Host MIPS or for general
nonvolatile storage. Many standard Nand Flash devices are supported, from 128 Mbit to 2 Gbit densities, and in x8 and x16
data widths. Hardware ECC, write protect, and local buffering assists with booting.
Synchronous burst read operations for an external FLASH ROM on the EBI bus is supported, which allows more code to
remain resident in the external EPROM chips instead of mirroring it to DRAM storage.
Internal bus protocols need to be extended to allow burst reads. The EBI interface converts these burst accesses into a
cache-line read of 16 bytes. Non-cacheable access would be handled as single word reads (as currently happens). This
allows the use of synchronous FLASH ROM chips, such as the Intel 28F256Kxx family.
