2/24/2008 9T6WP
Preliminary Hardware Data Module
BCM7405
06/29/07
Functional Description
Bro a d c o m Co rp o r a ti o n
Document
7405-1HDM00-R
Peripherals Page 1-89
A
DVANCED
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ONNECTIVITY
I
NTERFACE
Ethernet
The BCM7405 Ethernet Media Access Controller (MAC) provides physical media access through a Media Independent
Interface (MII) to either the internal 10/100 Ethernet transceiver or an external transceiver. In addition to basic Ethernet
access functions, the MAC provides statistic counters fully compliant with the following Management Information Base (MIB)
The statistics standards are RFC 1757, RFC 1643, and IEEE802.3. The MAC features include:
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802.3u compliant Transmit and Receive engines
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Separate Transmit and Receive FIFOs with programmable watermarks
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Full-duplex and Half-duplex Operation
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Full-duplex frame-based Flow Control compliant with 802.3x
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Four perfect match destination address (DA) filters with accept or reject capability
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Unicast and multicast DA filtering options
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Automatic CRC checking and generation
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Automatic padding of undersize transmit frames
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MII Management interface allows control of internal and external transceiver functions
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Internal Loopback
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Integrated MIB counters
The Ethernet MAC provides the control and protocol functions necessary for the transmission and reception of 802.3 data
streams. During transmission, packet data is removed from the transmit FIFO, framed with preamble and CRC, and
forwarded to the transceiver. During reception, the data is received from the transceiver, the frame’s destination address and
validity is checked, and packet data is placed into the receive FIFO.
Serial ATA Controller
The BCM7405 integrates a dual serial ATA disk drive control module and dual physical layer interfaces on chip. The dual
high-performance multiport SATA module contains two SATA 2.0 compliant controllers with integrated Physical layers and
connects directly to a PCI Bus (32/64 bit, 33/66 MHz) on the host side. The SATA module, shown in
, can communicate with any Serial ATA device on the device side, such as an SATA HDD, SATA port multiplier, or a
SATA-to-IDE bridge. High-performance DMA channels are provided on a per-port basis to maximize the system throughput.
Salient Features
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64-bit 66/133 MHz, PCIx compliant interface
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Two SATA-II (3.0 Gbps) Ports—SATA 2.0 compliant
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High-performance DMA engines per SATA channel—Peak throughput of 300 Mbps per channel
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Built-in end-to-end, at-speed production test support
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Integrated BERT and PRBS Engines for self-checking of the PHY and SerDes Interfaces
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Built-in self-test for FIFO RAM cores
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Supports 48-bit LBA
