2/24/2008 9T6WP
Preliminary Hardware Data Module
BCM7405
06/29/07
Functional Description
Bro a d c o m Co rp o r a ti o n
Document
7405-1HDM00-R
Peripherals Page 1-79
Arbitration process (required with multiple BSC masters). It is assumed that BCM7405 is the only device equipped with BSC
master capability.
BSC Master Interface Operation
This BSC master interface can be configured to perform four different combinations of transmitting (WRITE) and receiving
(READ) data from a slave device by setting appropriate data transfer format (DTF) of the control register:
•
Write only
•
Read only
•
Read then write combination
•
Write then read combination
BSC S
LAVE
This serial slave test interface block allows an external serial BSC master device to access internal chip slave devices and
external EBI slave devices during normal operation.
Any serial byte length transfer is supported.
The interface supports both big-endian or little-endian address ordering and byte packing.
The test interface block is a master device on the ISB interface.
BSC Operation
Full BSC and M-Bus compatible interface specifications define a wide range of addressing modes and protocols for use in
complex multi-master systems. The BSC test interface on the BCM7405 is a subset of these interfaces. General call
addresses and fast-mode (400 Kbps) operation and slave control of the serial clock for wait state control are not supported.
The BSC interface consists of the serial data (SDA) and serial clock (SCL) signals, which can control a large number of
devices on a common bus. The addressing of the different devices is accomplished through an established protocol on the
two-wire interface. In the general case for BSC devices, both SDA and SCL are bidirectional signals with open-drain output
drivers. This allows multiple devices to be connected to the bus in a wired and configuration with external pull-up resistors.
In this test interface, SDA is bidirectional, but SCL is always an input, since the interface acts as a slave device.
Data transfers are clocked by the SCL signal with one SCL pulse per bit of data. SDA is required to be stable during the high
period of the SCL signal. Transitions of SDA while SCL is high are used to signal the interface start (S), stop (P), and
repeated start (Sr) conditions.
The start condition (S) is defined as a high-to-low transition of SDA while SCL is high. The stop condition (P) is the low-to-
high transition of SDA while SCL is high. Data transmissions are always preceded by a start condition and end with a stop
condition and may contain repeated starts within the transmission to alter the direction of the data flow or to change the
register address.
All data transmission operations occur in 8-bit blocks. Each block is acknowledged by the designated receiver by an
acknowledge signal (A). This signal is generated on the 9th pulse of SCL for each block transferred.
The supported modes of operation are write and read.
